90 research outputs found

    Estimation of Analog Parametric Test Metrics Using Copulas

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    © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.International audienceA new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation

    Enrichment of limited training sets in machine-learning-based analog/RF Test

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    Abstract-This paper discusses the generation of informationrich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of low-cost measurements to a set of device performances and (b) grade such tests with parts per million (PPM) accuracy. This is achieved by sampling a non-parametric estimate of the joint probability density function of measurements and performances. Our case study is an ultra-high frequency receiver front-end and the focus of the paper is to learn the mapping between a lowcost test measurement pattern and a single pass/fail test decision which reflects compliance to all performances. The small fraction of devices for which such a test decision is prone to error are identified and retested through standard specification-based test. The mapping can be set to explore thoroughly the tradeoff between test escapes, yield loss, and percentage of retested devices

    SymBIST: Symmetry-based Analog/Mixed-Signal BIST

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    Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP

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    International audienceIn this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics

    Self-Testing Analog Spiking Neuron Circuit

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    International audienceHardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology

    Compact Functional Testing for Neuromorphic Computing Circuits

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    We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time. © 1982-2012 IEEE

    Statistical Learning for Analog Circuit Testing

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