Full chip modelling of ICs under CDM stress

In this thesis, CDM ESD stress on the Integrated Circuits (IC) and the various factors which affect the robustness of an IC design against CDM stress is investigated. One of the main reasons for CDM failure are the voltage gradients set across the circuit during CDM stress. The IC being also the source, its discharge current path is not constrained near the input and output pads as in other kinds of ESD stress. Instead it can be anywhere through the internal circuitry into the ground. The major hinderance in developing a CDM robust protection design is the lack of knowledge on the CDM current and its discharge path through the circuit. CDM withstand level, is package dependent and it is impossible to characterize a circuit design to be CDM robust independent of its package type

The influence of technology variation on ggNMOSTs and SCRs against CDM BSD stress

In this paper we present a systematic study on the effect of process and layout variation for grounded-gate NMOSTs and L VTSCRs in a 0.18μ,m technology under negative non-socketed Charged Device Model (CDM) stress. Failure Analysis of the stressed devices was done using Scanning Electron Microscopy (SEM). A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance ofL VTSCRs can be as good as that of ggNMOSTs under CDM stresses

Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels - An explantion and die protection strategy

With sownscaling of device dimensions and increased usage of automated handlers, Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major readon for field returns in the Integrated Circuit (IC) industry. In the case of CDM stress, the IC is both the source of static charge and part od the discharge path. Hence CDM test results are greatly affected by the nature of the package, pin position and the location of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to find the actual discharge current flowing through the die and the protection structures for different packages and pin positions. From this general protection strategy for CDM discharges, independent of the IC layout design is developed

Full chip model of CMOS Integrated Circuits under Charged Device Model stress

An ESD event which occurs when a charged IC touches a grounded surface is known as CDM type of ESD. The resulting static charge flow from CDM discharge causes large voltage overshoots across the IC causing gate-oxide damage. Measurements of exact internal voltage drops across the gate-oxide during CDM stress, is not possible because of the parasitic influence of the measurement set-up on the discharge path. This paper presents an efficient method of studying the voltage transients across the internal nodes of the IC during CDM stress, based circuit simulation. It presents a basic understanding of the charge flow during a CDM event, based on which an equivalent circuit model of the entire IC under CDM stress is developed. The correctness of the model is verified with the measurement data obtained for input protection structures in the 0.18μm CMOS technology node

Impact of layout and technology variation on the CDM performance of ggNMOSTs and SCRs

In this paper we present a systematic study on the effect of process and layout variation for groundedgate NMOSTs and LVTSCRs in a 0.18m technology under negative non-socketed Charged Device Model (CDM) stress. A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance of LVTSCRs can be as good as that of ggNMOSTs under CDM stresses

The influence of technology variation on ggNMOSTs and SCRs against CDM ESD stress

In this paper we present a systematic study on the effect of process and layout variation for grounded-gate NMOSTs and LVTSCRs in a 0.1

Study on the influence of package parasitics and substrate resistance on the Charged Device Model(CDM) failure levels - possible protection methodology

Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major reason for field returns in the Integrated Circuit (IC) industry especially with downscaling of device dimensions and increased usage of automated handlers. In the case of CDM stress, the IC is both the source of static charge and part of the discharge path. Hence CDM test results are greatly affected by the package properties and the distribution of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to compare the actual discharge current flowing through the die and the protection structures for two different package materials. A general protection methodology for the ICs during CDM event, applicable to all IC design types, is suggested

A 3-D circuit model to evaluate CDM performance of ICs

This paper presents a physical description of the static charge flow through an IC during a CDM event. Based on this description, an equivalent 3-D circuit to model the complete IC under CDM stress is proposed. The model takes into account various factors like package parasitics, substrate resistance, parasitic contacts of the circuit elements with the substrate, bus line resistances, distribution of protection devices. It allows studying the influence of these factors on the voltage transients seen across the gate-oxides of MOS transistors. CDM measurements on an IC with rail based protection showed gate-oxide failure at the MOS transistors in the internal core circuitry. The proposed circuit model is applied to study the voltage transients between the internal MOS transistors gate and local substrate during CDM stress and thereby explain the reason for the observed gate-oxide failure. It is found that VSS line contact distribution with the substrate rail enhances CDM robustness, provided the power lines (VSS and VDD line) are well clamped to each other