Mitral valve repair in heart failure

Mitral regurgitation (MR) is a frequent complication of end‐stage heart failure. Historically, these patients were either managed medically or with mitral valve replacement, both associated with poor outcomes. Mitral valve repair via an ‘undersized’ annuloplasty repair is safe and effectively corrects MR in heart‐failure patients. All of the observed changes contribute to reverse remodeling and restoration of the normal left‐ventricular geometric relationship. Mitral valve repair offers a new strategy for patients with MR and end‐stage heart failure.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/102643/1/ejhf00125-2.pd

Understanding the performance of concurrent error detecting superscalar microarchitectures

Superscalar out-of-order microarchitectures can be modified to support redundant execution of a program as two concurrent threads for soft-error detection. However, the extra workload from redundant execution incurs a performance penalty due to increased contention for resources throughout the datapath. We present four key parameters that affect performance of these designs, namely 1) issue and functional unit bandwidth, 2) issue queue and reorder buffer capacity, 3) decode and retirement bandwidth, and 4) coupling between redundant threads' instantaneous resource requirements. We then survey existing work in concurrent error detecting superscalar microarchitectures and evaluate these proposals with respect to the four factors. © 2005 IEEE

PAI: A lightweight mechanism for single-node memory recovery in DSM servers

Several recent studies identify the memory system as the most frequent source of hardware failures in commercial servers. Techniques to protect the memory system from failures must continue to service memory requests, despite hardware failures. Furthermore, to support existing OS's, the physical address space must be retained following reconfiguration. Existing techniques either suffer from a high performance overhead or require pervasive hardware changes to support transparent recovery. In this paper, we propose Physical Address Indirection (PAI), a lightweight, hardware-based mechanism for memory system failure recovery. PAI provides a simple hardware mapping to transparently reconstruct affected data in alternate locations, while maintaining high performance and avoiding physical address changes. With full-system simulation of commercial and scientific workloads on a 16-node distributed shared memory server, we show that prior techniques have an average degraded mode performance loss of 14% and 51% for commercial and scientific workloads, respectively. Using PAI's dataswap reconstruction, the same workloads have 1% and 32% average performance losses. © 2007 IEEE

Fingerprinting: Bounding the Soft-Error Detection Latency and Bandwidth

Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting, that detects differences in execution across a dual modular redundant (DMR) processor pair. Fingerprinting summarizes a processor's execution history in a hash- based signature; differences between two mirrored processors are exposed by comparing their fingerprints. Fingerprinting tightly bounds detection latency and greatly reduces the interprocessor communication bandwidth required for checking. This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection. The result of this study shows that fingerprinting is the only error detection mechanism that simultaneously allows high-error coverage, low error detection bandwidth, and high I/O performance

Fingerprinting: Bounding the Soft-Error Detection Latency and Bandwidth

Fingerprinting summarizes the history of internal processor state updates into a cryptographic signature. The processors in a dual modular redundant pair periodically exchange and compare fingerprints to corroborate each other's correctness. relative to other techniques, fingerprinting offers superior error coverage and significantly reduces the error-detection latency and bandwidth