Deployable Hook Retrieval System for UAV Rescue and Delivery

The rapid development of unmanned aerial vehicles (UAVs) has helped expand their practical use to many industrial applications. However, UAVs sometimes suffer from a flight time limitation and/or a loss in communication. Such undesired malfunctions can endanger public safety and incur economic losses. This paper presents a new class of UAV that can retrieve a disabled or malfunctioned UAV from the ground. We developed a deployable hook retrieval system (DHRS) which integrates three principal mechanisms (i.e., deployment, slider-linkage-release, and hook release). Each mechanism plays a role in deploying and retrieving multiple hooks while using a simple control strategy. Through a Finite Element Method simulation, the hook was topologically optimized in order to achieve a high strength while reducing weight. The deployed multiple hooks allow the device to capture the target regardless of its orientation. Due to these design strategies, object recognition using a computer vision was simply demonstrated by exploiting ORB and FLANN algorithms. Through an experimental study, we discussed the target range, success rate, and the practical uses that the DHRS could achieve. The results show that the proposed designs were versatile and consistently successful in capturing the targets while addressing constraints such as power consumption, computational load, and lack of prior knowledge or information about the target

Restructuring field layouts for embedded memory systems

Abstrac

Restructuring field layouts for embedded memory systems

In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remapping scheme for dynamically allocated structures in order to provide better locality than conventional field layouts. Our proposed scheme reduces cache miss rates drastically by aggregating and grouping fields from multiple instances of the same structure, which implies the performance improvement and power reduction. Our methodology will become more important in the design space exploration, especially as the embedded systems for data oriented application become prevalent. Experimental results show that average L1 and L2 data cache misses are reduced by 23 % and 17%, respectively. Due to the enhanced localities, our remapping achieves 13 % faster execution time on average than original programs. It also reduces power consumption by 18 % for data cache.