42 research outputs found

    Universal analytic model for tunnel FET circuit simulation

    Get PDF
    A simple analytic model based on the Kane-Sze formula is used to describe the current-voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate-source bias and the negative differential resistance for negative drain-source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junctio

    Characterization and control of unconfined lateral diffusion under stencil masks

    Get PDF
    A quantitative study of the spreading behavior of electron-beam-evaporated Al, Au, Cr, Ge, Pt, and Ti on oxidized Si substrates has been performed using translated stencil masks. At least two mechanisms are needed to account for the lateral spreading of the deposited materials: The deposition edge moves by a Fickian diffusion with a diffusion coefficient of 6.7nm2/s6.7nm2∕s at 45°C45°C which is approximately independent of the deposited material. Once under the stencil mask, the deposited material spreads 0.1–2μm0.1–2μm (at 45°C45°C for under 2h2h), in a thin layer as a result of surface diffusion. The evaporation in N2N2 or O2O2 at 50μTorr50μTorr significantly suppresses the spreading with Ti showing the greatest reduction of (7–8)×

    Foreword Special Issue on Transistors With Steep Subthreshold Swing for Low-Power Electronics

    Get PDF
    The increasing power consumption of integrated circuits is today the main impediment to the density scaling of integrated circuit technology. The reduction of supply voltage is the most effective way to reduce power; however, using modern transistors voltage reduction is traded against reduced speed or limited by a rising off-state leakage, neither of which is desirable. A better tradeoff can be achieved if the fundamental current control mechanism provides a steep turn-on characteristic. Steep means better than 60 mV/decade at room temperature, the limit obtained by barrier lowering in a bipolar transistor or metal oxide semiconductor field effect transistor (MOSFET) when the current is dominated by the thermionic emission of carriers above the energy barrier in the base or channel region

    Graphene as Transparent Electrode for Direct Observation of Hole Photoemission from Silicon to Oxide

    Full text link
    The outstanding electrical and optical properties of graphene make it an excellent alternative as a transparent electrode. Here we demonstrate the application of graphene as collector material in internal photoemission (IPE) spectroscopy; enabling the direct observation of both electron and hole injections at a Si/Al2O3 interface and successfully overcoming the long-standing difficulty of detecting holes injected from a semiconductor emitter in IPE measurements. The observed electron and hole barrier heights are 3.5 eV and 4.1 eV, respectively. Thus the bandgap of Al2O3 can be further deduced to be 6.5 eV, in close agreement with the valued obtained by vacuum ultraviolet spectroscopic ellipsometry analysis. The detailed optical modeling of a graphene/Al2O3/Si stack reveals that by using graphene in IPE measurements the carrier injection from the emitter is significantly enhanced and the contribution of carrier injection from the collector electrode is minimal. The method can be readily extended to various IPE test structures for a complete band alignment analysis and interface characterization.Comment: 15 pages, 5 figure
    corecore