Extending Static Synchronization Beyond SIMD and VLIW

A key advantage of SIMD (Single Instruction stream, Multiple Data stream) architectures is that synchronization is effected statically at compile-time, hence the execution-time cost of synchronization between “processes” is essentially zero. VLIW (Very Long Instruction Word) machines are successful in large part because they preserve this property while providing more flexibility in terms of what kinds of operations can be parallelized. In this paper, we propose a new kind of architecture —- the “static barrier MIMD” or SBM — which can be viewed as a further generalization of the parallel execution abilities of static synchronization machines. Barrier MIMDs are asynchronous Multiple Instruction stream Multiple Data stream architectures capable of parallel execution of loops, subprogram calls, and variable execution- time instructions; however, little or no run-time synchronization is needed. When a group of processors within a barrier MIMD has just encountered a barrier, any conceptual synchronizations between the processors are statically accomplished with zero cost — as in a SIMD or VLIW and using similar compiler technology. Unlike these machines, however, as execution continues the relative timing of processors may become less precisely knowable as a static, compile-time, quantity. Where this imprecision becomes too large, the compiler simply inserts a synchronization barrier to insure that timing imprecision at that point is zero, and again employs purely static, implicit, synchronization. Both the architecture and the supporting compiler technology are discussed in detail

Prospectus for a Remote PASM Execution and Debugging Environment - PDB

This document describes four design alternatives for a remote debugging and execution environment for the PASM Parallel Processing System Prototype in the School of EE at Purdue. Two alternatives involve acquisition of modest hardware for system enhancement, while the others are software-only solutions. All solutions involve use of a high-resolution bit-mapped graphics device, mouse and keyboard input, and a broad-band Ethernet-like communication medium. These latter components are currently available. The goal of this environment is to support any type of debugging which is currently supported by using the front panel of the machine and several terminals which are manually multiplexed between PEs and other resource management processors of the system. The environment will support voluntary output of processor activity from, and input to, any of the 30 processors of the PASM prototype. This configuration represents a step toward multiprogramming of the machine and will support development of software tools, languages and additional applications. Debugging information will be in the form of textual (or other) output displayed on virtual windows of a high-resolution device such as a SUN 3/50

The PASM parallel processing system: Hardware design and operating system concepts

Many of today\u27s scientific and industrial problems require enormous computing power. Since circuit switching speeds are reaching fundamental limits, avenues to speed up computations other than that using faster components are being explored. One such avenue is the use of parallelism. PASM is a dynamically reconfigurable SIMD/MIMD parallel processing system design for up to 1,024 processing elements (PEs). It can be dynamically reconfigured to work as one or more SIMD (single instruction stream - multiple data stream) and/or MIMD (multiple instruction stream - multiple data stream) machines. A prototype with 30 MC68000 microprocessors, including 16 PEs in the computational engine, has been designed and constructed. The design of the prototype hardware is described, as well as the design tradeoffs that were made. Extending the current prototype by the addition of a Network Interface Unit (NIU) to each PE is proposed. Such an NIU significantly enhances interprocessor communication by offloading communication overhead from the PE\u27s main CPU. One way to extend the prototype design to a system with 1,024 processors in the computational engine is presented. The powerful reconfiguration capabilities of PASM can be fully utilized only if all tradeoffs influencing reconfiguration are known. Attributes of the PASM architecture, operating system software, and potential application programs that affect both the cost and advantages of system reconfiguration are investigated. This information can be incorporated in a knowledge base for an Intelligent Operating System that automatically configures and reconfigures the PASM system to achieve optimum performance. One aspect of reconfiguration, task migration, is examined for systems that use a multistage cube network

Strategies for the Implementation of Interconnection Network Simulators on Parallel Computers

Methods for simulating multistage interconnection networks using massively parallel SIMD computers are presented. Aspects of parallel simulation of interconnection networks are discussed and different strategies of mapping the architecture of the network to be simulated onto the parallel machine are studied and compared. To apply these methods to a wide variety of network topologies, the discussions are based on general interconnection network and switch box models. As case studies, two strategies for mapping synchronous multistage cube networks on the MasPar MP-1 SIMD machine are explored and their implementations are compared. The methods result in a simulator implementation with which 10 9 data packets can be simulated in 40 minutes on the MasPar system. Keywords: mapping strategies, multistage interconnection networks, parallel simulation, parallel processing, SIMD machine, time-driven simulation * This research was supported in part by the German Science Foundation DFG scho..