Locally adaptive vector quantization: Data compression with feature preservation

A study of a locally adaptive vector quantization (LAVQ) algorithm for data compression is presented. This algorithm provides high-speed one-pass compression and is fully adaptable to any data source and does not require a priori knowledge of the source statistics. Therefore, LAVQ is a universal data compression algorithm. The basic algorithm and several modifications to improve performance are discussed. These modifications are nonlinear quantization, coarse quantization of the codebook, and lossless compression of the output. Performance of LAVQ on various images using irreversible (lossy) coding is comparable to that of the Linde-Buzo-Gray algorithm, but LAVQ has a much higher speed; thus this algorithm has potential for real-time video compression. Unlike most other image compression algorithms, LAVQ preserves fine detail in images. LAVQ's performance as a lossless data compression algorithm is comparable to that of Lempel-Ziv-based algorithms, but LAVQ uses far less memory during the coding process

Phased burst error-correcting array codes

Various aspects of single-phased burst-error-correcting array codes are explored. These codes are composed of two-dimensional arrays with row and column parities with a diagonally cyclic readout order; they are capable of correcting a single burst error along one diagonal. Optimal codeword sizes are found to have dimensions n1×n2 such that n2 is the smallest prime number larger than n1. These codes are capable of reaching the Singleton bound. A new type of error, approximate errors, is defined; in q-ary applications, these errors cause data to be slightly corrupted and therefore still close to the true data level. Phased burst array codes can be tailored to correct these codes with even higher rates than befor

On-Chip ECC for Multi-Level Random Access Memories

In this talk we investigate a number of on-chip coding techniques for the protection of Random Access Memories which use multi-level as opposed to binary storage cells. The motivation for such RAM cells is of course the storage of several bits per cell as opposed to one bit per cell [l]. Since the typical number of levels which a multi-level RAM can handle is 16 (the cell being based on a standard DRAM cell which has varying amounts of voltage stored on it) there are four bits recorded into each cell [2]. The disadvantage of multi-level RAMs is that they are much more prone to errors, and so on-chip ECC is essential for reliable operation. There are essentially three reasons for error control coding in multi-level RAMs: To correct soft errors, to correct hard errors, and to correct read errors. The source of these errors is, respectively, alpha particle radiation, hardware faults, and data level ambiguities. On-chip error correction can be used to increase the mean life before failure for all three types of errors. Coding schemes can be both bitwise and cellwise. Bitwise schemes include simple parity checks and SEC-DED codes, either by themselves or as product codes [3]. Data organization should allow for burst error correction, since alpha particles can wipe out all four bits in a single cell, and for dense memory chips, data in surrounding cells as well. This latter effect becomes more serious as feature sizes are scaled, and a single alpha particle hit affects many adjacent cells. Burst codes such as those in [4] can be used to correct for these errors. Bitwise coding schemes are more efficient in correcting read errors, since they can correct single bit errors and allow the remaining error correction power to be used elsewhere. Read errors essentially affect one bit only, since the use of Grey codes for encoding the bits into the memory cells ensures that at most one bit is flipped with each successive change in level. Cellwise schemes include Reed-Solomon codes, hexadecimal codes, and product codes. However, simple encoding and decoding algorithms are necessary, since excessive space taken by powerful but complex encoding/decoding circuits can be offset by having more parity cells and using simpler codes. These coding techniques are more useful for correcting hard and soft errors which affect the entire cell. They tend to be more complex, and they are not as efficient in correcting read errors as the bitwise codes. In the talk we will investigate the suitability and performance of various multi-level RAM coding schemes, such as row-column codes, burst codes, hexadecimal codes, Reed-Solomon codes, concatenated codes, and some new majority-logic decodable codes. In particular we investigate their tolerance to soft errors, and to feature size scaling

A static RAM chip with on-chip error correction

This paper describes a 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip). The chip employs the linear sum code (LSC) technique to perform error detection and correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with 3-µm feature size. Testing results of the actual chip shows a significant improvement in random error tolerance

Single Phased Burst Error Correcting Array Codes

Array codes composed of row and column parities with a diagonally cyclic readout order are capable of correcting a single burst error along one diagonal. A new equation which defines permissible array sizes is presented. These codes have an optimal size which is shown to be a number theoretic problem. In addition, correction of approximate errors is presented; this can be generalized for many classes of error correcting codes

Locally Adaptive Vector Quantization For Image Compression

In this paper we study various improvements to a locally adaptive vector quantization (LAVQ) algorithm. The effects of including bit stripping, index compression, and filtering techniques will be discussed. Software implementation and comparisons with non-adaptive vector quantization algorithms will be studied

A static RAM chip with on-chip error correction

This paper describes a 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip). The chip employs the linear sum code (LSC) technique to perform error detection and correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with 3-µm feature size. Testing results of the actual chip shows a significant improvement in random error tolerance

Glucocerebrosidases catalyze a transgalactosylation reaction that yields a newly-identified brain sterol metabolite, galactosylated cholesterol

?-Glucocerebrosidase (GBA) hydrolyzes glucosylceramide (GlcCer) to generate ceramide. Previously, we demonstrated that lysosomal GBA1 and nonlysosomal GBA2 possess not only GlcCer hydrolase activity, but also transglucosylation activity to transfer the glucose residue from GlcCer to cholesterol to form ?-cholesterylglucoside (?-GlcChol) in vitro. ?-GlcChol is a member of sterylglycosides present in diverse species. How GBA1 and GBA2 mediate ?-GlcChol metabolism in the brain is unknown. Here, we purified and characterized sterylglycosides from rodent and fish brains. Although glucose is thought to be the sole carbohydrate component of sterylglycosides in vertebrates, structural analysis of rat brain sterylglycosides revealed the presence of galactosylated cholesterol (?-GalChol), in addition to ?-GlcChol. Analyses of brain tissues from GBA2-deficient mice and GBA1- and/or GBA2-deficient Japanese rice fish (Oryzias latipes) revealed that GBA1 and GBA2 are responsible for ?-GlcChol degradation and formation, respectively, and that both GBA1 and GBA2 are responsible for ?-GalChol formation. Liquid chromatography?tandem MS revealed that ?-GlcChol and ?-GalChol are present throughout development from embryo to adult in the mouse brain. We found that ?-GalChol expression depends on galactosylceramide (GalCer), and developmental onset of ?-GalChol biosynthesis appeared to be during myelination. We also found that ?-GlcChol and ?-GalChol are secreted from neurons and glial cells in association with exosomes. In vitro enzyme assays confirmed that GBA1 and GBA2 have transgalactosylation activity to transfer the galactose residue from GalCer to cholesterol to form ?-GalChol. This is the first report of the existence of ?-GalChol in vertebrates and how ?-GlcChol and ?-GalChol are formed in the brain.Medical Biochemistr