123 research outputs found
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA
Efficient low complexity error correcting code(ECC) is considered as an
effective technique for mitigation of multi-bit upset (MBU) in the
configuration memory(CM)of static random access memory (SRAM) based Field
Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large
overhead and complex decoding circuit to correct adjacent multibit error. In
this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm
for error detection and parity based two dimensional Erasure Product Code for
error correction. Present error mitigation techniques perform error correction
in the CM without considering the criticality or the execution period of the
tasks allocated in different portion of CM. In most of the cases, error
correction is not done in the right instant, which sometimes either suspends
normal system operation or wastes hardware resources for less critical tasks.
In this paper,we advocate for a dynamic priority-based hardware scheduling
algorithm which chooses the tasks for error correction based on their area,
execution period and criticality. The proposed method has been validated in
terms of overhead due to redundant bits, error correction time and system
reliabilityComment: 6 pages, 8 figures, conferenc
FixPix: Fixing Bad Pixels using Deep Learning
Efficient and effective on-line detection and correction of bad pixels can
improve yield and increase the expected lifetime of image sensors. This paper
presents a comprehensive Deep Learning (DL) based on-line detection-correction
approach, suitable for a wide range of pixel corruption rates. A confidence
calibrated segmentation approach is introduced, which achieves nearly perfect
bad pixel detection, even with few training samples. A computationally
light-weight correction algorithm is proposed for low rates of pixel
corruption, that surpasses the accuracy of traditional interpolation-based
techniques. We also propose an autoencoder based image reconstruction approach
which alleviates the need for prior bad pixel detection and yields promising
results for high rates of pixel corruption. Unlike previous methods, which use
proprietary images, we demonstrate the efficacy of the proposed methods on the
open-source Samsung S7 ISP and MIT-Adobe FiveK datasets. Our approaches yield
up to 99.6% detection accuracy with <0.6% false positives and corrected images
within 1.5% average pixel error from 70% corrupted images
Voltage Scaled Low Power DNN Accelerator Design on Reconfigurable Platform
The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely Vivado with Xilinx Artix-7 FPGA and academic platform VTR with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in Vivado and VTR tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature
Optical property modification of ZnO: Effect of 1.2 MeV Ar irradiation
We report a systematic study on 1.2 MeV Ar^8+ irradiated ZnO by x-ray
diffraction (XRD), room temperature photoluminescence (PL) and
ultraviolet-visible (UV-Vis) absorption measurements. ZnO retains its wurtzite
crystal structure up to maximum fluence of 5 x 10^16 ions/cm^2. Even, the width
of the XRD peaks changes little with irradiation. The UV-Vis absorption spectra
of the samples, unirradiated and irradiated with lowest fluence (1 x 10^15
ions/cm^2), are nearly same. However, the PL emission is largely quenched for
this irradiated sample. Red shift of the absorption edge has been noticed for
higher fluence. It has been found that red shift is due to at least two defect
centers. The PL emission is recovered for 5 x 10^15 ions/cm^2 fluence. The
sample colour is changed to orange and then to dark brown with increasing
irradiation fluence. Huge resistivity decrease is observed for the sample
irradiated with 5 x 10^15 ions/cm^2 fluence. Results altogether indicate the
evolution of stable oxygen vacancies and zinc interstitials as dominant defects
for high fluence irradiation.Comment: Accepted in Physica Sattus Solidi (c
Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)
The massive amounts of data generated by camera sensors motivate data
processing inside pixel arrays, i.e., at the extreme-edge. Several critical
developments have fueled recent interest in the processing-in-pixel-in-memory
paradigm for a wide range of visual machine intelligence tasks, including (1)
advances in 3D integration technology to enable complex processing inside each
pixel in a 3D integrated manner while maintaining pixel density, (2) analog
processing circuit techniques for massively parallel low-energy in-pixel
computations, and (3) algorithmic techniques to mitigate non-idealities
associated with analog processing through hardware-aware training schemes. This
article presents a comprehensive technology-circuit-algorithm landscape that
connects technology capabilities, circuit design strategies, and algorithmic
optimizations to power, performance, area, bandwidth reduction, and
application-level accuracy metrics. We present our results using a
comprehensive co-design framework incorporating hardware and algorithmic
optimizations for various complex real-life visual intelligence tasks mapped
onto our P2M paradigm
Accelerating and pruning CNNs for semantic segmentation on FPGA
Semantic segmentation is one of the popular tasks in computer vision, providing pixel-wise annotations for scene understanding. However, segmentation-based convolutional neural networks require tremendous computational power. In this work, a fully-pipelined hardware accelerator with support for dilated convolution is introduced, which cuts down the redundant zero multiplications. Furthermore, we propose a genetic algorithm based automated channel pruning technique to jointly optimize computational complexity and model accuracy. Finally, hardware heuristics and an accurate model of the custom accelerator design enable a hardware-aware pruning framework. We achieve 2.44X lower latency with minimal degradation in semantic prediction quality (−1.98 pp lower mean intersection over union) compared to the baseline DeepLabV3+ model, evaluated on an Arria-10 FPGA. The binary files of the FPGA design, baseline and pruned models can be found in github.com/pierpaolomori/SemanticSegmentationFPGA
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