A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures

International audienceModern SoCs are characterized by increasing power density and consequently increasing temperature, that directly impacts performances, reliability and cost of a device through its packaging. Thermal issues need to be predicted and mitigated as early as possible in the design flow, when the optimization opportunities are the highest. In this paper, we present an efficient framework for the design of dynamic thermal mitigation schemes based on a high-level SystemC virtual prototype tightly coupled with efficient power and thermal simulation tools. We demonstrate the benefit of our approach through silicon comparison with the SThorm 64-core architecture and provide simulation speed results making it a sound solution for the design of thermal mitigation early in the flow

Design of Hardened Embedded Systems on Multi-FPGA Platforms

International audienceThe aim of this article is the definition of a reliability-aware methodology for the design of embedded systemson multi-FPGA platforms. The designed system must be able to detect the occurrence of faults globally andautonomously, in order to recover or to mitigate their effects. Two categories of faults are identified, basedon their impact on the device elements; (i) recoverable faults, transient problems that can be fixed withoutcausing a lasting effect namely and (ii) nonrecoverable faults, those that cause a permanent problem, makingthe portion of the fabric unusable. While some aspects can be taken from previous solutions available inliterature, several open issues exist. In fact, no complete design methodology handling all the peculiar issuesof the considered scenario has been proposed yet, a gap we aim at filling with our work. The final systemexposes reliability properties and increases its overall lifetime and availabilit

Fault Classification for SRAM-Based FPGAs in theSpace Environment for Fault Mitigation

This letter proposes a classification algorithm to discriminate between recoverable and not recoverable faults occurring in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), with the final aim of devising a methodology to enable the exploitation of these devices also in space applications, typically characterized by long mission times, where permanent faults become an issue. By starting from a characterization of the radiation effects and aging mechanisms, we define a controller able to classify such faults and consequently to apply the appropriate mitigation strategy

Automated Resource-aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems

The floorplanning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider both the constraints imposed by the heterogeneous distribution of the resources in the devices and the reconfiguration capabilities. In fact, current-generation FPGAs present a complex architecture, but also offer more sophisticated reconfiguration features. The proposed floor- planner, based on an accurate model of the devices, takes into account all these elements and finds an optimal solution, suitable for reconfigurable designs

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms

This paper presents an approach for increasing the lifetime of systems implemented on SRAM-based FPGAs, by introducing fault tolerance properties enabling the system to autonomously manage the occurrence of both transient and permanent faults. On the basis of the foreseen mission time and application environment, the designer is supported in the implementation of a system able to reconfigure itself, either by reloading the correct configuration in case of transient faults, or by relocating part of the functionality in presence of permanent faults. The result is a system implementation offering good performance and correct functionality even when faults occur. The proposed approach is evaluated in a case study to highlight the overall characteristics of the final implementation

A novel design methodology for implementingreliability-aware systems on SRAM-based FPGAs

This paper presents a novel design flow for the implementation of digital systems onto SRAM-based FPGAs with soft error mitigation properties. Traditional fault detection/tolerance techniques are coupled with the device dynamic reconfiguration property to achieve soft error mitigation capabilities, and are applied to the single component, to groups of components or to the entire system, based on the most convenient trade-off with respect to a set of parameters. The design flow performs a two-steps multiobjective design space exploration, driven by a cost function taking into account resource utilization, area, and reconfiguration time. A floorplanning based on precise FPGA resource models is introduced to guarantee the feasibility of the hardened solution, identifying a convenient mapping onto the heterogeneous reconfigurable fabric. Experimental results show that the achieved solutions, aimed at achieving a prompt, "on demand” recovery when fault occurs, are characterized by a reduction in reconfiguration time that is higher than 80 percent, a significant improvement with respect to classical solutions

A Reliable Fault Classifier for Dependable Systems on SRAM-based FPGAs

This paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones, for critical applications, such as the ones in the space environment. In this scenario, we investigate the reliable implementation of the fault classification algorithm, that can be so integrated in an overall reliable system

Data traffic management in a reconfigurable Network-on-Chip for Dynamic Neural Networks

National audienceDeep neural networks (DNNs) play an important role in modern applications. The growing need for their deployment on the edge led to the development of many low-power hardware architectures to accelerate inference. However, those architectures mostly target conventional static DNN models and do not implement features to directly address the challenges of dynamic models. This paper introduces a methodology for data traffic management in a reconfigurable Network-on-Chip (NoC) for the implementation of a Dynamic Neural Network (DyNN)

Data traffic management in a reconfigurable Network-on-Chip for Dynamic Neural Networks

National audienceDeep neural networks (DNNs) play an important role in modern applications. The growing need for their deployment on the edge led to the development of many low-power hardware architectures to accelerate inference. However, those architectures mostly target conventional static DNN models and do not implement features to directly address the challenges of dynamic models. This paper introduces a methodology for data traffic management in a reconfigurable Network-on-Chip (NoC) for the implementation of a Dynamic Neural Network (DyNN)