The Upgrade I of LHCb VELO -- towards an intelligent monitoring platform

The Large Hadron Collider beauty (LHCb) detector is designed to detect decays of b- and c- hadrons for the study of CP violation and rare decays. At the end of the LHC Run 2, many of the LHCb measurements remained statistically dominated. In order to increase the trigger yield for purely hadronic channels, the hardware trigger will be removed, and the detector will be read out at 40 MHz. This, in combination with the five-fold increase in luminosity, requires radical changes to LHCb's electronics, and, in some cases, the replacement of entire sub-detectors with state-of-the-art detector technologies. The Vertex Locator (VELO) surrounding the interaction region is used to reconstruct the collision points (primary vertices) and decay vertices of long-lived particles (secondary vertices). The upgraded VELO will be composed of 52 modules placed along the beam axis divided into two retractable halves. The modules will each be equipped with 4 silicon hybrid pixel tiles, each read out by 3 VeloPix ASICs. The total output data rate anticipated for the whole detector will be around 1.6 Tbit/s. The highest occupancy ASICs will have pixel hit rates of approximately 900 Mhit/s, with the corresponding output data rate of 15 Gbit/s. The LHCb upgrade detector will be the first detector to read out at the full LHC rate of 40 MHz. The VELO upgrade will utilize the latest detector technologies to read out at this rate while maintaining the required radiation-hard profile and minimizing the detector material

Phase I Upgrade of the Readout System of the Vertex Detector at the LHCb Experiment

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of 40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at 5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above 900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware