An Improved linearity ring oscillator-based current-to-digital converter

Many biosensors produce single-ended current outputs. Lab-on-chip applications demand parallel readout channels requiring low area current-to-digital converters. High HD2 has limited the current controlled ring oscillator’s (CCROs) adoption as a low area, single-ended converter. This work improves CCRO open loop linearity by 10 dB. A wide-bandwidth current buffer is also designed. A low area (0.0025 mm 2 ), low power ( 357 μW ), single-ended, and 1 MHz bandwidth converter suitable for array readout is presented with the measured performance

A 7-bit 7-GHz multiphase interpolator-based DPC for CDR applications

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply

A 7-bit 7-GHz multiphase interpolator-based DPC for CDR applications

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM's Vp. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flipchipped on top of the Silicon Photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only. (C) 2017 Optical Society of Americ