Quasi-digital low-dropout voltage regulators uses controlled pass transistors

This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version

Linear-assisted DC/DC regulator-based current source for LED drivers

© The Institution of Engineering and Technology 2016. A proposal of current source based on a linear-assisted DC/DC converter is presented, in which a linear voltage regulator assists a switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e. high efficiency (similar to the switching converter), and low output ripple and fast reaction to the load changes (similar to the linear regulator). To reduce the power dissipation in the linear regulator, it is considered as an assisted circuit for providing just a little fraction of the load current. Furthermore, this stage provides the required clock signal for the switching counterpart, resulting in reduction of the complexity in the design of the control scheme for the switching converter and a compact topology, especially for onchip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance current-source drivers for LED technology in lighting applications. The implementation and results indicate that the proposed linear-assisted DC/DC regulator-based current source can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives.Postprint (published version

Four–quadrant linear–assisted DC/DC voltage regulator

This Mixed Signal Letter presents a proposal of four-quadrant linear-assisted DC/DC voltage regulator. In this topology, a class-AB linear voltage amplifier assists a four-quadrant switching DC/DC converter in order to obtain a compact circuit with advantages of both alternatives; i.e., high efficiency, inherent in switching converters, and low output ripple and fast reaction to the load changes that are characteristics of linear regulators. In order to reduce the power dissipation in the linear regulator, it is considered as an assisting circuit for providing just a small fraction of the total load current. Furthermore, this stage provides the required clock signal for the switching counterpart, obtaining a compact topology thanks to the reduction of the complexity in the design of the control scheme for the switching converter. In fact, the proposed topology can be addressed to on-chip practical implementations, since no output capacitors are required. This last advantage provides the possibility of obtaining good-performance power-supply modulators for envelope tracking techniques in power amplifiers. The implementation and results indicate that the proposed four-quadrant linear-assisted DC/DC regulator can achieve a notably compacting and higher performance, while consuming less power in comparison to linear alternatives.Postprint (author's final draft

5GHz CMOS all-pass filter-based true time delay cell

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process.Postprint (published version

Quasi–digital low–dropout voltage regulators uses controlled pass transistors

This article presents a low quiescent current outputcapacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version

Tunable wide-band second-order all-pass filter-based time delay cell using active inductor

This paper presents a CMOS RF second-order voltage-mode all-pass filter (APF) as a time delay cell. The proposed filter benefits from a simple structure; consisting of one transistor, three resistors, and one grounded capacitor and inductor. The filter reaches a group delay of 60 ps over a 10 GHz bandwidth, while achieving maximum delay-bandwidth-product (DBW) and it consumes only 10.3 mW power. On the other hand, an active inductor is used in the APF instead of a passive RLC tank in order to control the time delay and improve the size. In this case, the power consumption increases while time delay can be tuned. The proposed APF is designed and simulated in a TSMC 180 nm CMOS process.Postprint (published version

Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022

Non peer reviewe

Design and implementation of a sliding-mode controller for digital low-dropout/linear regulators

This paper presents an approach to utilize of sliding-mode (SM) controller in digital low-dropout/linear regulators. Various design aspects, including the extraction of the regulator state-space model and sliding coefficients by considering the hitting, existence, and stability conditions are described. Moreover, the freeze control block is introduced as a solution to compensate the high frequency chattering phenomenon of SM, resulting in reduction of switching losses. In order to verify the statements, a quasi digital low-dropout/linear regulator (QDLDO) is implemented in a discrete form on a PCB. The circuit consists of the proposed current-mode current feedback amplifier (CFA)-based SM controller and switchedmode PMOS array driven by a bidirectional serial shift register, which is controlled by the SM controller. The results reveal that the controller detects the load changes rapidly, and eliminates the output limit-cycle oscillation, providing a robust and stable output voltage.Peer ReviewedPostprint (author's final draft

Low power output-capacitorless class-AB CMOS LDO regulator

Peer ReviewedPostprint (published version

CMOS RF first-order all-pass filter

In this paper, a wide-band first-order voltage-mode all-pass filter is presented. Due to a simple structure and appropriate performance of the proposed all-pass filter, this filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 4.5 GHz. The proposed circuit demonstrates a high linearity and consumes merely 16 mW power from a 1.8-V supply. Simulation results indicate an input-referred 1-dB compression point P1dB of 4.1 dBm and the wide-band operation capability of the first order all-pass filter. Furthermore, the proposed all-pass filter is capable of converting into a second-order all-pass filter adding only a grounded capacitor. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a TSMC 180-nm CMOS process.Postprint (published version