Depletion-mode Quantum Dots in Intrinsic Silicon

We report the fabrication and electrical characterization of depletion-mode quantum dots in a two-dimensional hole gas (2DHG) in intrinsic silicon. We use fixed charge in a SiO$_2$/Al$_2$O$_3$ dielectric stack to induce a 2DHG at the Si/SiO$_2$ interface. Fabrication of the gate structures is accomplished with a single layer metallization process. Transport spectroscopy reveals regular Coulomb oscillations with charging energies of 10-15 meV and 3-5 meV for the few- and many-hole regimes, respectively. This depletion-mode design avoids complex multilayer architectures requiring precision alignment, and allows to adopt directly best practices already developed for depletion dots in other material systems. We also demonstrate a method to deactivate fixed charge in the SiO$_2$/Al$_2$O$_3$ dielectric stack using deep ultraviolet light, which may become an important procedure to avoid unwanted 2DHG build-up in Si MOS quantum bits.Comment: Accepted to Applied Physics Letters. 5 pages, 3 figure

Shuttling an electron spin through a silicon quantum dot array

Coherent links between qubits separated by tens of micrometers are expected to facilitate scalable quantum computing architectures for spin qubits in electrically-defined quantum dots. These links create space for classical on-chip control electronics between qubit arrays, which can help to alleviate the so-called wiring bottleneck. A promising method of achieving coherent links between distant spin qubits consists of shuttling the spin through an array of quantum dots. Here, we use a linear array of four tunnel-coupled quantum dots in a 28Si/SiGe heterostructure to create a short quantum link. We move an electron spin through the quantum dot array by adjusting the electrochemical potential for each quantum dot sequentially. By pulsing the gates repeatedly, we shuttle an electron forward and backward through the array up to 250 times, which corresponds to a total distance of approximately 80 {\mu}m. We make an estimate of the spin-flip probability per hop in these experiments and conclude that this is well below 0.01% per hop.Comment: 11 pages, 3 main figures, 6 appendix figure

A fabrication guide for planar silicon quantum dot heterostructures

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.Comment: Accepted for publication in Nanotechnology. 31 pages, 12 figure

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a $^{28}$Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick $^{28}$Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29$\pm$0.02 $\mu$eV/sqrt(Hz) at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to cz-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system

Single-electron tunneling through an individual arsenic dopant in silicon

We report the single-electron tunneling behaviour of a silicon nanobridge where the effective island is a single As dopant atom. The device is a gated silicon nanobridge with a thickness and width of ∼20 nm, fabricated from a commercially available silicon-on-insulator wafer, which was first doped with As atoms and then patterned using a unique CMOS-compatible technique. Transport measurements reveal characteristic Coulomb diamonds whose size decreases with gate voltage. Such a dependence indicates that the island of the single-electron transistor created is an individual arsenic dopant atom embedded in the silicon lattice between the source and drain electrodes, and furthermore, can be explained by the increase of the localisation region of the electron wavefunction when the higher energy levels of the dopant As atom become occupied. The charge stability diagram of the device shows features which can be attributed to adjacent dopants, localised in the nanobridge, acting as charge traps. From the measured device transport, we have evaluated the tunnel barrier properties and obtained characteristic device capacitances. The fabrication, control and understanding of such “single-atom” devices marks a further step towards the implementation of single-atom electronics