Spawning aggregation of bigeye trevally, Caranx sexfasciatus, highlights the ecological importance of oil and gas platforms

Open Access via the Elsevier Agreement Acknowledgements We gratefully acknowledge the field and logistical support provided by the Crew of the Resolution. This research project was funded by Chevron through its Anchor Partnership with the UK National Decommissioning Centre. We also acknowledge in-kind support from Net Zero Technology Centre and the University of Aberdeen through their partnership in the UK National Decommissioning Centre.Peer reviewedPublisher PD

Child presence detection system and technologies

Child Presence Detection (CPD) is a safety system designed to assist drivers to prevent the consequences of mistakenly left children in closed parked vehicles. Recently, ASEAN NCAP has released its 2021-2025 Roadmap that outlines the implementation of CPD technology as an initiative to prevent such incidences from happening in the future. This paper aims to provide an overview of these CPD systems and their associated technologies that are readily embedded in vehicles, or commercially available in the market

Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance

High-Level Synthesis (HLS) is the process of developing digital circuits from behavioral specifications. It involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the controller synthesis. Evolutionary Algorithms have been already effectively applied to HLS to find good solution in presence of conflicting design objectives. In this paper, we present an evolutionary approach to HLS that extends previous works in three respects: (i) we exploit the NSGA-II, a multi-objective genetic algorithm, to fully automate the design space exploration without the need of any human intervention, (ii) we replace the expensive evaluation process of candidate solutions with a quite accurate regression model, and (iii) we reduce the number of evaluations with a fitness inheritance scheme. We tested our approach on several benchmark problems. Our results suggest that all the enhancements introduced improve the overall performance of the evolutionary search

Coordinated parallelizing compiler optimizations and high-level synthesis

We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a presynthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the SPARK framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing too], validate the utility of our approach to the behavioral synthesis of designs with complex control flows

Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits

The quality of high-level synthesis results for designs with complex and nested conditionals and loops can be improved significantly by employing speculative code motions. In this paper, we present two novel techniques that add scheduling steps to the branch of a conditional construct with the fewer scheduling steps. This ``balances'' or equalizes the number of scheduling steps in the conditional branches and increases the scope for application of speculative code motions. We apply these branch balancing techniques ``dynamically'' during scheduling. We implemented algorithms for the dynamic branch balancing techniques in a C-to-VHDL high-level synthesis framework called SPARK. We demonstrate the utility of these techniques by presenting results for experiments on four designs derived from two moderately complex applications, namely, MPEG-1 and the GIMP image processing tool. These results show that the two branch balancing techniques can reduce the cycles on the longest path through the design by up to 38% and the number of states in the controller by up to 37%