Neighbors of knots in the Gordian graph

We show that every knot is one crossing change away from a knot of arbitrarily high bridge number and arbitrarily high bridge distance.Comment: Accepted by American Mathematical Monthly. New version incorporates referee comment

Intangible capital and the investment-q relation

The neoclassical theory of investment has mainly been tested with physical investment, but we show that it also helps explain intangible investment. At the firm level, Tobin’s q explains physical and intangible investment roughly equally well, and it explains total investment even better. Compared with physical capital, intangible capital adjusts more slowly to changes in investment opportunities. The classic q theory performs better in firms and years with more intangible capital: Total and even physical investment are better explained by Tobin’s q and are less sensitive to cash flow. At the macro level, Tobin’s q explains intangible investment many times better than physical investment. We propose a simple, new Tobin’s q proxy that accounts for intangible capital, and we show that it is a superior proxy for both physical and intangible investment opportunities

An Engineering Learning Community To Promote Retention And Graduation Of At-Risk Engineering Students

Retention and graduation rates for engineering disciplines are significantly lower than desired, and research literature offers many possible causes. Engineering learning communities provide the opportunity to study relationships among specific causes and to develop and evaluate activities designed to lessen their impact. This paper details an engineering learning community created to combat three common threats to academic success of engineering students: financial difficulties, math deficiencies, and the lack of a supportive engineering culture. The project tracks participants in the learning community from first year through graduation to assess the effectiveness of its activities in improving retention and graduation rates. Scholarships were made available to address the financial difficulties; tutors, mentors, study groups, and a “freshman-to-sophomore bridge” summer program were provided to address math deficiencies; cohort engineering courses, active learning techniques, required group meetings, required group study sessions, dedicated study space, and dedicated faculty advisors were used to promote a sense of community. Quantitative retention and graduation rates for the cohort are compared to other engineering groups at the same institution. Qualitative results collected via student surveys and interviews, and lessons learned by project administrators are also presented. Retention and graduation rates of the cohort are better than those of comparable groups at the same institution. Graduation rates based upon freshman math placement are also higher than comparable groups.

STRS SpaceWire FPGA Module

An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface