Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF

Performance analysis of ultrathin junctionless double gate vertical MOSFETs

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability

Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design

This project investigates and analyzes the impact of process parameter variance on the drive current (ION) and leakage current (IOFF) for 19nm WSi2/TiO2 NMOS device using 2k-factorial design. The four process parameter, namely halo implant dose, halo implant energy, source/drain (S/D) implant dose and S/D implant energy will be investigated and adjusted to improve the results. The simulated of the device was performed by using ATHENA module. Meanwhile the electrical characterization of the device was implemented by using ATLAS module. These two modules will be combined with 2kfactorial to aid design and optimize the process parameters. The most effective process parameter with respect ION and IOFF were chosen depending on the percentage of the factor effect on S/N ratio that indicates the relative power of factor to reduce variation. The most dominant or significant factors in S/N Ratio are pocket halo implant dose and S/D implant energy. Meanwhile, the values of ION and IOFF values for 19nm WSi2/SiO2 NMOS device after optimization approaches are 591.38 µA/µm and 2.217 pA/µm respectively. The results obtained are meet the requirement of International Technology Roadmap Semiconductor (ITRS) 2013 prediction