Numerical exploration of spiking neuron circuits in organic pOTFT technology

International audienceSpike-based neural networks have been shown to hold more computational power than other architectures and their integration into mainstream computing is projected to herald a new age for information technology. Implementation using a flexible Thin Organic Large Area Electronics TOLAE process is a promising low cost way to integrate neuromorphic circuits into sensors, however its feasibility has never been demonstrated. Here we design and simulate a spiking neuron circuit that can be implemented using pOTFT TOLAE processes. Our spiking neuron circuit is inspired by the Morris-Lecar model. Two transistors model the flow in or out of ions onto a simulated membrane potential, two capacitors provide distinct time constants for the two competing processes and support circuits direct an excitation current towards the control transistors. The transistors are operated in the deep subthreshold regime at V < |3.5V| and currents ranging from 10 pA and 5 nA. To determine the appropriate dimensions and model parameters for the transistors in the circuit, we performed a systematic fitting of 210 devices fabricated at the CEA. We thus are able to demonstrate numerically a spiking neuron circuit in an existing organic technology. We also explore how variability in transistor size, the subthreshold swing and the turn on voltage effects the circuits. We consider both whether the transistors exhibits spiking behaviour and the range of this behaviour. Our results demonstrate the feasibility of OTFT technologies for spiking neuromorphic hardware

Characterization of the effective mobility by split C(V) technique in sub 0.1µm Si and SiGe PMOSFETs

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Interface oxide trap characterisation in germanium-on-insulator 0.12 &#x03BC;m PMOS transistors by drain current noise measurements

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Retention time enhancement in FD 1T-DRAM.

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Investigation of 1/f noise in germanium-on-insulator 0.12μm PMOS transistors from weak to strong inversion

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1/ f noise analysis in high mobility polymer-based OTFTs with non-fluorinated dielectric

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Mobility of strained and unstrained short channel MOSFETs: New insight by magnetoresistance

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Mobility characterization in advanced FD-SOI CMOS devices

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Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

International audienceIn this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current. Then, an activation energy criterion is used to determine the bias conditions that are appropriate to correct application of this method. Experimental values of “tunneling” field and tunneling parameter are extracted, with better reliability than with previous methods. Reliable extractions of the GIDL parameters enable to characterize junction quality independently of junction abruptness and of the impact of traps in the bandgap. This method is successfully applied and results are in agreement with expected results

Improved GeOI substrates for pMOSFET off-state leakage control

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