Improving NDT with Automatic Test Case Generation

The model-driven development defi nes the software development process as a set of iterations to create models and a set of transformations to obtain new models. From this point of view, this paper presents the enhancement of a model- driven approach, called navigational development techniques (NDT), by means of new models and transformations in order to generate test cases. It also states some conclusions from the research work and practical cases in which this approach was used.Ministerio de Ciencia e Innovación TIN2010-20057-C03-02Ministerio de Ciencia e Innovación TIN 2010-12312-

Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology

Pruebas de aceptación orientadas al usuario. Contexto ágil para un proyecto de gestión Documental

Las pruebas de aceptación representan aquella fase del ciclo de vida de desarrollo de software en el que el equipo de desarrollo y el área usuaria de un sistema de información tienen que garantizar que el sistema desarrollado se corresponde con los requerimientos definidos. En equipos multidisciplinares, como en el caso de los sistemas de gestión documental que involucra a documentalistas, archiveros, ingenieros informáticos, etc., es una fase que hay que planificar de manera adecuada y a la que hay que dotar con los mecanismos de gestión adecuados para garantizar su correcta ejecución. En este trabajo se propone la adaptación de un mecanismo ágil, basado en la metodología Scrum, que da una importancia alta a esta fase, de manera que se propone ir abordándola de manera incremental, no dejando la ejecución de dicha fase para el final del desarrollo, ofreciendo así mecanismos de detección precoz de inconsistencias funcionales. Esta propuesta ha sido desarrollada en el contexto del proyecto THOT (Proyecto de innovación de la gestión documental aplicada a expedientes de contratación de servicios y obras de infraestructuras de transporte), desarrollado por la Universidad de Sevilla para la Agencia de Obra Pública de la Junta de Andalucía. El artículo, muestra su aplicación en este contexto.Acceptance tests represent the phase of the software development life cycle in which the development team and the user area of an information system must ensure that the developed system fulfils the defined requirements. In multidisciplinary teams, like is the case of document management systems that involve filmmakers, archivists and computer engineers among others, this is a phase that must be properly planned and must provide the most suitable management mechanisms to ensure proper execution. This paper presents the adaptation of an agile mechanism based on the Scrum methodology, giving high importance to this phase. So, it is proposed to perform this phase incrementally, preventing this phase to be executed only at the end of development and providing mechanisms for early detection of functional inconsistencies. This approach has been developed within the context of THOT (Innovation project management applied to document records recruitment services and transport infrastructure projects), developed by the University of Seville for the Public Works Agency project of the Junta de Andalucía. This paper shows its application in this context

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS

Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-μm CMOS technology.European Union IST 2001 38097Ministerio de Ciencia y Tecnología TIC 2003 09817 C02 01Office of Naval Research (USA) N00014021088

Programmable retinal dynamics in a CMOS mixed-signal array processor chip

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5μm CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 × 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.Office of Naval Research (USA) N00014-00-10429European Community IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

CMOS realization of a 2-layer CNN universal machine chip

Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the possibilities of these complex spatio-temporal dynamics in image processing, a prototype chip has been developed by implementing this CNN model with analog signal processing blocks. This chip has been designed in a 0.5/spl mu/m CMOS technology. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 /spl times/ 10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Office of Naval Research (USA) N-00014-00-1-0429Comisión Interministerial de Ciencia y Tecnología TIC-1999-082

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics

A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway which renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5/spl times/10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Comisión Interministerial de Ciencia y Tecnología TIC1999-082

Model-driven Test Engineering: A Practical Analysis in the AQUA-WS Project

The effective application of test phases has been one of the most relevant, critical and cost phases in the life cycle of software projects in the last years. During the test phase, the test team has to assure the quality of the system and the concordance with the initial requirements of the system. The model driven paradigm is offering suitable results in some areas and the test phase could be one of them. This paper presents how the application of this paradigm can help to improve this aspect in the functional test generation and it analyses the experience in a real project developed under this approach.Ministerio de Ciencia e Innovación TIN2010-20057-C03-02Ministerio de Ciencia e Innovación TIN 2010-12312-EJunta de Andalucía TIC-578

Current Social Perception of and Value Attached to Nursing Professionals’ Competences: An Integrative Review

In order to develop nurses’ identities properly, they need to publicise their professional competences and make society aware of them. For that, this study was conducted to describe the competences that society currently attributes to nursing professionals and how nursing is valued in society. This review was based on the conceptual framework by Whittemore and Knafl. The literature search was conducted using PubMed, WOS, and CINAHL databases, and the search strategy was based on a combination of natural language and standardised keywords, with limits and criteria for inclusion, exclusion, and quality. The results of the studies were classified and coded in accordance with the competence groups of the professional profile described in the Tuning Educational Structures in Europe programme. Fourteen studies were selected. The most commonly reported competence groups were as follows: nursing practice and clinical decision making; and communication and interpersonal competences. Nursing is perceived as a healthcare profession dedicated to caring for individuals. Its other areas of competence and its capacity for leadership are not well known. In order to develop a professional identity, it is essential to raise awareness of the competences that make up this professional profile

Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator

Many FPGAs vendors have recently included embedded processors in their devices, like Xilinx with ARM-Cortex A cores, together with programmable logic cells. These devices are known as Programmable System on Chip (PSoC). Their ARM cores (embedded in the processing system or PS) communicates with the programmable logic cells (PL) using ARM-standard AXI buses. In this paper we analyses the performance of exhaustive data transfers between PS and PL for a Xilinx Zynq FPGA in a co-design real scenario for Convolutional Neural Networks (CNN) accelerator, which processes, in dedicated hardware, a stream of visual information from a neuromorphic visual sensor for classification. In the PS side, a Linux operating system is running, which recollects visual events from the neuromorphic sensor into a normalized frame, and then it transfers these frames to the accelerator of multi-layered CNNs, and read results, using an AXI-DMA bus in a per-layer way. As these kind of accelerators try to process information as quick as possible, data bandwidth becomes critical and maintaining a good balanced data throughput rate requires some considerations. We present and evaluate several data partitioning techniques to improve the balance between RX and TX transfer and two different ways of transfers management: through a polling routine at the userlevel of the OS, and through a dedicated interrupt-based kernellevel driver. We demonstrate that for longer enough packets, the kernel-level driver solution gets better timing in computing a CNN classification example. Main advantage of using kernel-level driver is to have safer solutions and to have tasks scheduling in the OS to manage other important processes for our application, like frames collection from sensors and their normalization.Ministerio de Economía y Competitividad TEC2016-77785-