15,488 research outputs found

    Flux form Semi-Lagrangian methods for parabolic problems

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    A semi-Lagrangian method for parabolic problems is proposed, that extends previous work by the authors to achieve a fully conservative, flux-form discretization of linear and nonlinear diffusion equations. A basic consistency and convergence analysis are proposed. Numerical examples validate the proposed method and display its potential for consistent semi-Lagrangian discretization of advection--diffusion and nonlinear parabolic problems

    Throughput-driven floorplanning with wire pipelining

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    The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires

    Adaptive Latency Insensitive Protocols

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    Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

    On-Chip Transparent Wire Pipelining (invited paper)

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    Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from being a straightforwardly applicable technique, this methodology requires a number of design modifications in order to insert it seamlessly in the current design flow. In this paper we briefly survey the methods presented by other researchers in the field and then we thoroughly analyze the solutions we recently proposed, ranging from system-level wire pipelining to physical design aspects

    A new system design methodology for wire pipelined SoC

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    Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural changes are needed to preserve functionality. We illustrate a proposal that, while allowing the use of IP blocks without modification, takes advantage of a minimal knowledge of the IP's communication profile to dramatically increase the performances. We showed the formal equivalence between WP and original system and proved the higher performance achievable through a relevant case study

    Hamiltonian linearization of the rest-frame instant form of tetrad gravity in a completely fixed 3-orthogonal gauge: a radiation gauge for background-independent gravitational waves in a post-Minkowskian Einstein spacetime

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    In the framework of the rest-frame instant form of tetrad gravity, where the Hamiltonian is the weak ADM energy E^ADM{\hat E}_{ADM}, we define a special completely fixed 3-orthogonal Hamiltonian gauge, corresponding to a choice of {\it non-harmonic} 4-coordinates, in which the independent degrees of freedom of the gravitational field are described by two pairs of canonically conjugate Dirac observables (DO) raˉ(τ,σ⃗)r_{\bar a}(\tau ,\vec \sigma), πaˉ(τ,σ⃗)\pi_{\bar a}(\tau ,\vec \sigma), aˉ=1,2\bar a = 1,2. We define a Hamiltonian linearization of the theory, i.e. gravitational waves, {\it without introducing any background 4-metric}, by retaining only the linear terms in the DO's in the super-hamiltonian constraint (the Lichnerowicz equation for the conformal factor of the 3-metric) and the quadratic terms in the DO's in E^ADM{\hat E}_{ADM}. {\it We solve all the constraints} of the linearized theory: this amounts to work in a well defined post-Minkowskian Christodoulou-Klainermann space-time. The Hamilton equations imply the wave equation for the DO's raˉ(τ,σ⃗)r_{\bar a}(\tau ,\vec \sigma), which replace the two polarizations of the TT harmonic gauge, and that {\it linearized Einstein's equations are satisfied} . Finally we study the geodesic equation, both for time-like and null geodesics, and the geodesic deviation equation.Comment: LaTeX (RevTeX3), 94 pages, 4 figure

    Issues in Implementing Latency Insensitive Protocols

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    The performance of future Systems-on-Chip will be limited by the latency of long interconnects requiring more than one clock cycle for the signals to propagate. To deal with the problem L. Carloni et alii proposed the Latency Insensitive Protocols (LIP). A design that works under the assumption of zero-delay connections between functional modules is modified in a Latency Insensitive Design (LID) by encapsulating them within wrappers (“shells”) and connecting them through internally pipelined blocks (“relay stations”) complying with a protocol that guarantees identity of behavior [1]. The wrappers perform:- Data Validation: each output channel signals whether the datum therein present has still to be consumed.- Back Pressure: when the pearl is stopped the shell generates a stop signal sent in the opposite direction of inputs;- Clock Gating: a module waiting for new data and/or stopped keeps its present state. Such a protocol was implemented [2] through the introductio
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