Data analysis / BEBR No. 540

Includes bibliographical references."In any comprehensive research project, there are essentially five steps. First, one starts with a literature review with regard to a particular research question. Second, one seeks to develop a theory. Third, the research question is finalized, frequently in the form of a hypothesis to be tested. Fourth, data are collected. Fifth, the subject matter of this paper, the data are analyzed in order to come to a resolution of the research question. There are two general approaches to analyzing research data. If the data were gathered concerning a 'research question,' a description of the data may be sufficient. However, if the data were gathered to accept or reject a formal hypothesis, statistical analysis is usually in order. This paper briefly surveys the principal data analysis methodologies that are available.

Profile Guided Dataflow Transformation for FPGAs and CPUs

This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43 %. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation

RIPL: An Efficient Image Processing DSL for FPGAs

Field programmable gate arrays (FPGAs) can accelerate image processing by exploiting fine-grained parallelism opportunities in image operations. FPGA language designs are often subsets or extensions of existing languages, though these typically lack suitable hardware computation models so compiling them to FPGAs leads to inefficient designs. Moreover, these languages lack image processing domain specificity. Our solution is RIPL, an image processing domain specific language (DSL) for FPGAs. It has algorithmic skeletons to express image processing, and these are exploited to generate deep pipelines of highly concurrent and memory-efficient image processing components.Comment: Presented at Second International Workshop on FPGAs for Software Programmers (FSP 2015) (arXiv:1508.06320

Syllabus for "Basics for Advanced Mathematics"

Investigations of arithmetic textbooks were conducted to determine what the authors considered important and essential to a good arithmetic course. An effort was made to discover correlations among the texts. Listed, in no particular sequence, were my beliefs of what was important and essential in such a course. These essentials were: Vocabulary, definitions, self explanatory explanations, practical and understandable examples, varied and numerous practice problems, homework problems, and reliable suggested tests. Due to the recent trend to introduce Modern Mathematics in the Secondary Schools, consideration was given to a more practical course which would include the use of letter symbols, a study of right triangles, and uses of exponents and radicals. None of the texts were considered adequate. Excellent illustrations and explanations of certain topics were paraphrased and included in this report. All of the authors agreed that a good course in arithmetic began with an understanding of the four operations of arithmetic. Most of the texts started with a study of fractions. Some of the texts had ample problems and satisfactory methods of explanations. None of them contained a satisfactory amount of material on all the essentials suggested by the author. This conclusion verified a previously studied conclusion and provided the stimulus for the preparation of this report, which the author believes will result in a textbook suitable and adequate for the times.Natural Scienc

Science and Engineering Serials: Issues and Challenges in the Electronic Environment

Pricing Issues: The Core Problem. Subscription Price Increases. Fluctuations in the Foreign Exchange Rate. ISI Impact Factors, Journal Quality, and Cost-Effectiveness. Questions of Content, Archiving, and Access.. Conclusion. Reference Notes

Power efficient dataflow design for a heterogeneous smart camera architecture

Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low

Profile driven dataflow optimisation of mean shift visual tracking

Profile guided optimisation is a common technique used by compilers and runtime systems to shorten execution runtimes and to optimise locality aware scheduling and memory access on heterogeneous hardware platforms. Some profiling tools trace the execution of low level code, whilst others are designed for abstract models of computation to provide rich domain-specific context in profiling reports. We have implemented mean shift, a computer vision tracking algorithm, in the RVC-CAL dataflow language and use both dynamic runtime and static dataflow profiling mechanisms to identify and eliminate bottlenecks in our naive initial version. We use these profiling reports to tune the CPU scheduler reducing runtime by 88%, and to optimise our dataflow implementation that reduces runtime by a further 43% - an overall runtime reduction of 93%. We also assess the portability of our mean shift optimisations by trading off CPU runtime against resource utilisation on FPGAs. Applying all dataflow optimisations reduces FPGA design space significantly, requiring fewer slice LUTs and less block memory

The Big Shill

Shills are people who endorse products and companies for pay, while pretending that their endorsements are ingenuous. Here we argue that there is something objectionable about shilling that is not reducible to its bad consequences, the lack of epistemic conscientiousness it often relies upon, or to the shill's insincerity. Indeed, we take it as a premise of our inquiry that shilling can sometimes be sincere, and that its wrongfulness is not mitigated by the shill's sincerity, in cases where the shill is sincere. Our proposal is that the shill's defining characteristic is their knowingly engaging in a kind of speech that obscures a certain aspect of its social status—most commonly, by pretending to speak on their own personal behalf, while in fact speaking as an employee—and that this sort of behaviour is objectionable irrespective of any other features of the shill's conduct. This sort of obfuscation undermines a socially beneficial communicative custom, in which we conscientiously mark the distinction between personal speech and speech‐for‐hire

p53-mediated neurodegeneration in the absence of the nuclear protein Akirin2.

Proper gene regulation is critical for both neuronal development and maintenance as the brain matures. We previously demonstrated that Akirin2, an essential nuclear protein that interacts with transcription factors and chromatin remodeling complexes, is required for the embryonic formation of the cerebral cortex. Here we show that Akirin2 plays a mechanistically distinct role in maintaining healthy neurons during cortical maturation. Restricting Akirin2 loss to excitatory cortical neurons resulted in progressive neurodegeneration via necroptosis and severe cortical atrophy with age. Comparing transcriptomes from Akirin2-null postnatal neurons and cortical progenitors revealed that targets of the tumor suppressor p53, a regulator of both proliferation and cell death encoded b

14-3-3 Proteins Interact with a Hybrid Prenyl-Phosphorylation Motif to Inhibit G Proteins

Signaling through G proteins normally involves conformational switching between GTP- and GDP-bound states. Several Rho GTPases are also regulated by RhoGDI binding and sequestering in the cytosol. Rnd proteins are atypical constitutively GTP-bound Rho proteins, whose regulation remains elusive. Here, we report a high-affinity 14-3-3-binding site at the C terminus of Rnd3 consisting of both the Cys241-farnesyl moiety and a Rho-associated coiled coil containing protein kinase (ROCK)-dependent Ser240 phosphorylation site. 14-3-3 binding to Rnd3 also involves phosphorylation of Ser218 by ROCK and/or Ser210 by protein kinase C (PKC). The crystal structure of a phosphorylated, farnesylated Rnd3 peptide with 14-3-3 reveals a hydrophobic groove in 14-3-3 proteins accommodating the farnesyl moiety. Functionally, 14-3-3 inhibits Rnd3-induced cell rounding by translocating it from the plasma membrane to the cytosol. Rnd1, Rnd2, and geranylgeranylated Rap1A interact similarly with 14-3-3. In contrast to the canonical GTP/GDP switch that regulates most Ras superfamily members, our results reveal an unprecedented mechanism for G protein inhibition by 14-3-3 proteins