Molecular Electronics – Resonant Transport through Single Molecules

The mechanically controllable break-junction technique (MCBJ) enables us to investigate charge transport through an individually contacted and addressed molecule in ultra-high vacuum (UHV) environment at variable temperature ranging from room temperature down to 4 K. Using a statistical measurement and analysis approach, we acquire current–voltage (I-V) characteristics during the repeated formation, manipulation, and breaking of a molecular junction. At low temperatures, voltages accessing the first molecular orbitals in resonance can be applied, providing spectroscopic information about the junction's energy landscape, in particular about the molecular level alignment in respect to the Fermi energy of the electrodes. Thereby, we can investigate the non-linear transport properties of various types of functional molecules and explore their potential use as functional building blocks for future nano-electronics. An example will be given by the reversible and controllable switching between two distinct conductive states of a single molecule. As a proof-of-principle for functional molecular devices, a single-molecule memory element will be demonstrated

Toward Nanowire Electronics

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs

Single photon emission and detection at the nanoscale utilizing semiconductor nanowires

We report recent progress toward on-chip single photon emission and detection in the near infrared utilizing semiconductor nanowires. Our single photon emitter is based on a single InAsP quantum dot embedded in a p-n junction defined along the growth axis of an InP nanowire. Under forward bias, light is emitted from the single quantum dot by electrical injection of electrons and holes. The optical quality of the quantum dot emission is shown to improve when surrounding the dot material by a small intrinsic section of InP. Finally, we report large multiplication factors in excess of 1000 from a single Si nanowire avalanche photodiode comprised of p-doped, intrinsic, and n-doped sections. The large multiplication factor obtained from a single Si nanowire opens up the possibility to detect a single photon at the nanoscale.Comment: 11 pages, 7 figure

Transition to the quantum hall regime in InAs nanowire cross-junctions

We present a low-temperature electrical transport study on four-terminal ballistic InAs nanowire cross-junctions in magnetic fields aligned perpendicular to the cross-plane. Two-terminal longitudinal conductance measurements between opposing contact terminals reveal typical 1D conductance quantization at zero magnetic field. As the magnetic field is applied, the 1D bands evolve into hybrid magneto-electric sub-levels that eventually transform into Landau levels for the widest nanowire devices investigated (width = 100 nm). Hall measurements in a four-terminal configuration on these devices show plateaus in the transverse Hall resistance at high magnetic fields that scale with (ve 2 /h) -1 . e is the elementary charge, h denotes Planck's constant and v is an integer that coincides with the Landau level index determined from the longitudinal conductance measurements. While the 1D conductance quantization in zero magnetic field is fragile against disorder at the NW surface, the plateaus in the Hall resistance at high fields remain robust as expected for a topologically protected Quantum Hall phase. © 2019 IOP Publishing Ltd

Deterministic assembly of linear gold nanorod chains as a platform for nanoscale applications

We demonstrate a method to assemble gold nanorods highly deterministically into a chain formation by means of directed capillary assembly. This way we achieved straight chains consisting of end-to-end aligned gold nanorods assembled in one specific direction with well-controlled gaps of [similar]6 nm between the individual constituents. We determined the conditions for optimum quality and yield of nanorod chain assembly by investigating the influence of template dimensions and assembly temperature. In addition, we transferred the gold nanorod chains from the assembly template onto a Si/SiO2 target substrate, thus establishing a platform for a variety of nanoscale electronic and optical applications ranging from molecular electronics to optical and plasmonic devices. As a first example, electrical measurements are performed on contacted gold nanorod chains before and after their immersion in a solution of thiol end-capped oligophenylenevinylene molecules showing an increase in the conductance by three orders of magnitude, indicating molecular-mediated transport

III-V compound semiconductor transistors—from planar to nanowire structures

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS application

Benchmarking energy consumption and latency for neuromorphic computing in condensed matter and particle physics

The massive use of artificial neural networks (ANNs), increasingly popular in many areas of scientific computing, rapidly increases the energy consumption of modern high-performance computing systems. An appealing and possibly more sustainable alternative is provided by novel neuromorphic paradigms, which directly implement ANNs in hardware. However, little is known about the actual benefits of running ANNs on neuromorphic hardware for use cases in scientific computing. Here we present a methodology for measuring the energy cost and compute time for inference tasks with ANNs on conventional hardware. In addition, we have designed an architecture for these tasks and estimate the same metrics based on a state-of-the-art analog in-memory computing (AIMC) platform, one of the key paradigms in neuromorphic computing. Both methodologies are compared for a use case in quantum many-body physics in two dimensional condensed matter systems and for anomaly detection at 40 MHz rates at the Large Hadron Collider in particle physics. We find that AIMC can achieve up to one order of magnitude shorter computation times than conventional hardware, at an energy cost that is up to three orders of magnitude smaller. This suggests great potential for faster and more sustainable scientific computing with neuromorphic hardware.Comment: 7 pages, 4 figures, submitted to APL Machine Learnin

Selective Area Growth of PbTe Nanowire Networks on InP

Hybrid semiconductor–superconductor nanowires are promising candidates as quantum information processing devices. The need for scalability and complex designs calls for the development of selective area growth techniques. Here, the growth of large scale lead telluride (PbTe) networks is introduced by molecular beam epitaxy. The group IV-VI lead-salt semiconductor is an attractive material choice due to its large dielectric constant, strong spin-orbit coupling, and high carrier mobility. A crystal re-orientation process during the initial growth stages leads to single crystalline nanowire networks despite a large lattice mismatch, different crystal structure, and diverging thermal expansion coefficient to the indium phosphide (InP) substrate. The high quality of the resulting material is confirmed by Hall bar measurements, indicating mobilities up to 5600 cm2 (Vs)−1, and Aharonov–Bohm experiments, indicating a low-temperature phase coherence length exceeding 21 µm. Together, these properties show the high potential of the system as a basis for topological networks.</p