Electrical tests at wafer level on bipolar/CMOS/DMOS technology for reliability purpose

International audienc

Reliability Oriented Process and Device Simulations of Power VDMOS transistors in Bipolar/CMOS/DMOS technology

International audienc

HCI degradation model based on the diffusion equation including the MVHR model

International audienceThis paper presents an improvement of the R-D model explaining analytically the 0.5 exponent observed during HCI stress. An original model based on diffusion equation is proposed where the balance between the hot-hole-induced generation of dangling bonds and the passivation mechanisms via a Multi-Vibrational Hydrogen Release is enlightened. The second and smaller slope observed is explained and modelled with the hot spot displacement along the Si-SiO2 interface

Reliatibility Oriented Process and Device Simulations of Power VDMOS transistors in Bipolar/CMOS/DMOS technology

International audienc

Degradation mechanism understanding of NLDEMOS SOI in RF applications

International audienceThe distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation

Robustness improvement of VDMOS transistors in bipolar/CMOS/DMOS technology

International audienc

Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology

International audienceThis paper presents results of reliability investigation of 20 V N-Drift MOS transistor in 0.13 μm CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, Vds limited and Vgs limited applications in order to improve circuit designs. For Vds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carrier injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor

Reliability improvement of high value doped polysilicon-based resistors

PosterInternational audienc

Electrical properties of high value doped polysilicon-based resistors

International audienc