One-by-one trap activation in silicon nanowire transistors

Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been identified as the main source of noise at low frequency. It often originates from an ensemble of a huge number of charges trapping and detrapping. However, a deviation from the well-known model of 1/f noise is observed for nanoscale MOSFETs and a new model is required. Here, we report the observation of one-by-one trap activation controlled by the gate voltage in a nanowire MOSFET and we propose a new low-frequency-noise theory for nanoscale FETs. We demonstrate that the Coulomb repulsion between electronically charged trap sites avoids the activation of several traps simultaneously. This effect induces a noise reduction by more than one order of magnitude. It decreases when increasing the electron density in the channel due to the electrical screening of traps. These findings are technologically useful for any FETs with a short and narrow channel.Comment: One file with paper and supplementary informatio

DEGRADATION OF SHORT-CHANNEL MOS TRANSISTORS STRESSED AT LOW TEMPERATURE

Nous étudions le vieillissement à 77 K de transistors MOS de type N soumis à de fortes contraintes électriques : tension de drain Vd = 5,5 V et tension de grille Vg variant de 1,5 à 6,5 V. Nous montrons que les maxima de la dégradation de transconductance et du décalage de la tension de seuil ne se manifestent pas pour les mêmes conditions de contrainte. Les résultats sont expliqués par la nature plus ou moins localisée des défauts créés qui est aussi responsable de la distorsion des courbes de transconductance et de son augmentation temporaire lors du vieillissement. Une augmentation inhabituelle de la transconductance en régime de saturation est également mise en évidence.Hot-carrier stressing was carried out on 1 µm n-type MOSFETs at 77 K with fixed drain voltage Vd = 5.5 V and gate voltage Vg varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation and threshold voltage shift do not occur at the same Vg. This behavior is explained by the localized nature of induced defects which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress. An anomalous increase in the saturation transconductance is also reported

Strain-enhanced performance of Si-Nanowire FETs

International audienc

HOT ELECTRON RELIABILITY OF DEEP SUBMICRON MOS TRANSISTORS

Nous étudions la dégradation des performances des transistors MOS ultra-courts (0.3 µm - 0.6 µm) engendrée par l'injection de porteurs chauds. Ces dispositifs ont un canal N, une structure conventionnelle (non LDD) et ont été optimisés pour fonctionner à 3 V. Plusieurs types de contraintes out été analysés. Un suivi systématique des paramètres importants a été réalisé en cours de vieillissement, la dégradation étant ensuite évaluée par des méthodes de caractérisation fine. L'influence des tensions d'alimentation sur la durée de vie des dispositifs est étudiée. Ces résultats sont interprétés en tenant compte de l'extension de la zone de défauts et du taux de génération locale d'états d'interface.The hot electron induced degradation of fully optimized N-channel MOSFET's, having channel lengths in the range 0.3 µm - 0.6 µm, is systematically investigated. The created defects and their influence on the device performance are evaluated with very sensitive techniques and explained using 2D modelling. The device lifetime is analysed as a function of the biasing conditions. These results are interpreted by taking into consideration the extension of the defective region as well as the local generation rate of interface states

Low temperature investigation of electrical conduction in polysilicon: simulation and experiment

51-54Nanograin polysilicon low temperature stochastic Coulomb oscillations Monte Carlo simulationInvestigation of electrical conduction in polysilicon nanowires (polySiNW) with nanograins (5 to 20nm), based on Monte Carlo (MC) simulations and electrical measurements from 4K to 300K are presented. Some irregular Coulomb Oscillations (CO) are observed at temperatures lower than 200K showing several period widths due to the random distribution in grain size (5-20nm). A remarkable result consists in more effective oscillations observed at intermediate range of temperatures (between 25K and 150K) and high drain voltages. The temperature dependence of COs is explained by the fact that in a multiple asymmetric dot system at low temperature, COs are observed not at the lowest but at an intermediate temperature range, whereas the drain voltage dependence is due to an enhanced non-resonant tunneling. MC simulations have confirmed experimental observations

Assessment of technological device parameters by low-frequency noise investigation in SOI omega-gate nanowire NMOS FETs

session 5: Device CharacterizationInternational audienceWe report an experimental investigation of oxide/channel interface quality in SOI omega-gate nanowire NMOS FETs with cross-section as small as 10nm×10nm by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, H 2 anneal, or channel orientation. A method for rigorous contribution assessment of the two interfaces (top surface vs. side-walls) is also demonstrated. Excellent quality of the interfaces is extracted for all our technological and structural parameters