A 40nm, high bandwidth, VCO-based burst-mode receiver backend for EHF multi-carrier wireless

A receiver back-end in 40 nm CMOS for an EHF wireless multi-carrier applications is presented. The system is designed to reduce the bandwidth of a multi-tone I/Q decomposed wideband signal after which it is digitized and stored. The bandwidth reduction is applied by means of a reconfigurable sub-sampling operation. The integrated ADCs, performing the digitization, are a time-based dual 128-phase VCO topology implementation. On-chip data buffering of 96 kB is foreseen, capable of storing burst signals of a duration up to 8 μs. The IC is capable to process discrete spectra up to an RF bandwidth of 6 GHz originating from a downconverted 60 GHz signal. A measured effective resolution of 6 bits is realized thanks to the inherent first order noise shaping of the built-in ADC. The SFDR is measured at 40 dB. Power consumption for the complete I/Q core, sampling at 3 GHz, is measured to be 106 mW. The area of the 40nm core is 0.162 mm2. © 2013 IEEE.status: publishe

High Resolution Time-of-Arrival for a cm-precise super 10 meter 802.15.3C-based 60 GHz OFDM Positioning Application

A 802.15.3c-compatible technique for super 10 meter cm-accurate and precise ranging is introduced, achieving update rates of more than 300 kHz. The implementation is realized on top of the 802.15.3c PHY High-Speed-Interface mode, specifying a multi-carrier orthogonal frequency division multiplexed (OFDM) implementation. The aimed application conditions foresee strong discrete non-line-of-sight fading conditions. The system’s performance is evaluated over these strong channel conditions. Due to the high absorption in the 60 GHz band and thus the poor signal-to-noise ratio at super 10 m distances the algorithm should be noise tolerant. The algorithm combines a classic auto correlation with the MLS-Prony method, a high resolution technique for frequency content analysis.status: publishe

Joint Estimation of Propagation Delay Dispersion and Time of Arrival in a 40nm CMOS Comparator Bank for Time-Based Receivers

This brief presents an approach to compensate time-of-arrival (ToA) estimation errors caused by the effect of signal depending propagation delays in receivers for ranging applications. As a straightforward reasoning, reducing the ToA error results in increased power consumption in the analog-front-end blocks of such receivers. In the proposed system topology, the asynchronous receiver's analog-front-end blocks contain an array of identical continuous-time comparators, which makes it suitable for a joint modeling approach and today's low-supply voltages. Attention is paid to tuning the nonstrobed comparator topology to make it suitable for this joint modeling. Using the comparator model in a least-squares-based algorithmic approach can reduce the ToA error (accuracy improvement) to nearly zero. A ToA systematic error reduction of 28 is faced for the ToA figure. Furthermore, energy consumption is more related to the activity of the ranging events, which makes this an interesting approach for ranging measurement rates of less than 1 MHz.status: publishe

TOWARDS A FAST AND HARDWARE EFFICIENT SUB-MM PRECISION RANGING SYSTEM

A sub-mm ranging system, which estimates the time of flight of a RF signal between two nodes using Time of Arrival (ToA) estimation, is possible according to maximum likelihood estimator simulations and theoretical bounds on ToA estimation. In this paper we propose a frequency domain based ToA estimator for an indoor ranging system which is broken into 3 computational steps towards an efficiently implementable estimator. Performance of this hardware efficient estimator is comparable with the maximum likelihood estimator’s and it is computationally efficient. Complexity of the computational steps can be traded off against each other. Moreover, the implementation-aware estimator provides high flexibility on choosing between transmitted signal energy, computational cost and precision of the ranging algorithm. In this work, a simulation precision better than 1 mm is obtained for SNRs below 0 dB, by transmitting an OFDM (Orthogonal Frequency Division Multiplexing) like signal whose duration is 9 μs, with a 6 GHz bandwidth on a 60 GHz carrier.status: publishe

Presilicon Circuit-Aware Linear Least Squares Spectral Analysis for Time-Based Data Converters

Presilicon time-based data converter spectral analysis usually incurs long simulation times. This brief shows an approach for the estimation of the data converter's spectral components and noise floor based on a small simulation window. Additionally, it provides two useful estimates of the technique's expected accuracy. The method is based on circuit-aware linear least squares spectral analysis. It can be applied together with the accuracy estimate and knowledge of the noise spectrum's shape during the design time of time-based data converters. It provides a significant advantage over classic fast Fourier transform-based techniques for time-based data converters. Both a theoretical background and simulation results are provided for a voltage-controlled oscillator (VCO)-based analog-to-digital (A/D) converter. The technique provides a good accuracy for both the spectral components and the data converter's noise floor. The accuracy estimate expresses the technique's performance, achieving a worst case error of only 5 dB, which proves its usability. © 2004-2012 IEEE.status: publishe