Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM

Adaptivity and Reconfigurability in Wireless Communications

A key issue of future wireless communication systems is that they have to be adaptive. In the Adaptive Wireless Networking (AWGN) project we aim at the implementation of adaptive wireless communication systems in a heterogeneous reconfigurable System-on-a-Chip (HRSoC). We introduce our methodologies for analyzing and mapping DSP functionality in dynamically reconfigurable heterogeneous hardware. A possible implementation of a multi-mode communication system in the MONTIUM architecture is discussed. Suggestions for future activities in the Adaptive Wireless Networking project are also given

Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture

Implementation of Multi-standard Wireless Communication Receivers in a Heterogeneous Reconfigurable System-on-Chip

Future mobile terminals become multi-mode communication systems. In order to handle different standards, we propose to perform baseband processing in heterogeneous reconfigurable hardware. Not only the baseband processing but also error decoding differs for every communication system. We already proposed implementations of the baseband processing part of an OFDM receiver and a Wideband CDMA receiver in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. Now, we also implemented an adaptive Viterbi decoder in the same coarse-grained MONTIUM architecture. The rate, constraint length and decision depth of the decoder can be adjusted to different communication systems. We show that the flexibility in the coarse-grained reconfigurable architecture is more than 200 times as energy-efficient compared to a general purpose solution but only 24 times less efficient compared to a dedicated solution

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient