Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation

International audience— This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an NMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of an NMOS transistor. It reveals the possible activation change of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation

On the Investigation of a Novel Dual-Control-Gate Floating Gate Transistor for VCO Applications

A new MOS device called Dual-Control Gate Floating Gate Transistor (DCG-FGT) is used as a building block in analog design. This device offers new approaches in circuit design and allows developing new functionalities through two operating modes: Threshold Voltage Adjustable Mode, where the DCG-FGT behaves like a MOS transistor with an electrically adjustable threshold voltage. Mixer Signal Mode where the DCG-FGT can mix two independent signals on its floating gate. This device is developed to be fully compliant with CMOS Non Volatile Memory (NVM) process. An electrical model of the DCG-FGT has been implemented in an electrical simulator to be available for analog design. A DCG-FGT based ring oscillator is studied in this paper

On the Investigation of a Novel Dual-Control-Gate Floating Gate Transistor for VCO Applications

A new MOS device called Dual-Control Gate Floating Gate Transistor (DCG-FGT) is used as a building block in analog design. This device offers new approaches in circuit design and allows developing new functionalities through two operating modes: Threshold Voltage Adjustable Mode, where the DCG-FGT behaves like a MOS transistor with an electrically adjustable threshold voltage. Mixer Signal Mode where the DCG-FGT can mix two independent signals on its floating gate. This device is developed to be fully compliant with CMOS Non Volatile Memory (NVM) process. An electrical model of the DCG-FGT has been implemented in an electrical simulator to be available for analog design. A DCG-FGT based ring oscillator is studied in this paper

Electrothermal Analyses of Bandpass NGD RLC-Network Topologies

This paper develops an original study of temperature effect on the unfamiliar bandpass (BP) negative group delay (NGD) lumped passive circuits. The paper presents the first study of electrothermal analysis of electronic circuits classified as BP-NGD topologies. The considered BP-NGD passive cells are mainly constituted by RLC-resonant networks. The equivalence between two basic BP-NGD topologies constituted by RLC-series and RLC-parallel networks is elaborated via the voltage transfer function (VTF) analogy. Then, the theoretical demonstrations are introduced to define the main specifications as the NGD center frequency, NGD value, attenuation and NGD bandwidth. The electrothermal innovative study is developed based on the temperature coefficient resistor (TCR) of elements constituting the BP-NGD circuits. With proofs of concept of RLC-series and RLC-parallel circuits operating with -500 ns NGD value at 13.56 MHz, calculated and simulated results showing are in excellent agreement. The sensitivity analyses of BP-NGD specifications in function of ambient temperature variation from 0°C to 100°C are investigated. The BP-NGD response variations versus frequency and temperature are characterized with thermo-frequency cartographies and discussed

NMOS transistors based Karsilayan & Schaumann gyrator: lowpass and bandpass filter applications'

International audienc

Design Considerations Towards Zero-Variability Resistive RAMs in HRS State

International audienceResistive RAM (RAM) intrinsic variability is widely recognized as a major hurdle for widespread adoption of the technology. Moreover, the deeper we go into the High Resistance State (HRS), the higher the variability. In this context, this paper proposes circuit level design strategies to mitigate HRS variability. During the RESET operation, the programming current is strictly controlled while the voltage across the RRAM cell is regulated. From a design standpoint, a write termination circuit is used to constantly sense the programming current and stop the RESET pulse when the preferred RESET current is reached. The write termination is combined with a voltage regulator which provides a strict control of the RESET voltage. The paper first reviews the RRAM variability phenomenon. Then, an optimized programming scheme is developed to control the HRS state to approach zero-variability. Compared to the classical fixed-pulse programming scheme, variability is reduced by 99%

Multi-band inductor-less VCO for IoT applications

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A CMOS Digitally Controlled Oscillator for Reconfigurable RF Applications

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Particle Identification and Tracking by the Use of a Pixel-Based Semiconductor Radiation Detector Coupled with Voltage Controlled Oscillators

A particle detection chain based on a CMOS SOI VCO circuit associated to a matrix of detection is presented. The solution is optimized for the recognition and tracking of various particles. Two ions are considered: an alpha and an aluminum. These two ions were chosen because there are very different in terms of energy and LET variations