Optimization and synchronization of programmable quantum communication channels

Quantum applications transmit and receive data through quantum and classical communication channels. Channel capacity, the distance and the photon path between transmitting and receiving parties and the speed of the computation links play an essential role in timely synchronization and delivery of information using classical and quantum channels. In this study, we analyze and optimize the parameters of the communication channels needed for the quantum application to successfully operate. We also develop algorithms for synchronizing data delivery on classical and quantum channels.Comment: 7 pages, 2 figure

Performance Evaluation of Sparse Matrix Multiplication Kernels on Intel Xeon Phi

Intel Xeon Phi is a recently released high-performance coprocessor which features 61 cores each supporting 4 hardware threads with 512-bit wide SIMD registers achieving a peak theoretical performance of 1Tflop/s in double precision. Many scientific applications involve operations on large sparse matrices such as linear solvers, eigensolver, and graph mining algorithms. The core of most of these applications involves the multiplication of a large, sparse matrix with a dense vector (SpMV). In this paper, we investigate the performance of the Xeon Phi coprocessor for SpMV. We first provide a comprehensive introduction to this new architecture and analyze its peak performance with a number of micro benchmarks. Although the design of a Xeon Phi core is not much different than those of the cores in modern processors, its large number of cores and hyperthreading capability allow many application to saturate the available memory bandwidth, which is not the case for many cutting-edge processors. Yet, our performance studies show that it is the memory latency not the bandwidth which creates a bottleneck for SpMV on this architecture. Finally, our experiments show that Xeon Phi's sparse kernel performance is very promising and even better than that of cutting-edge general purpose processors and GPUs

Characterization Of Thermal Stresses And Plasticity In Through-Silicon Via Structures For Three-Dimensional Integration

Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in the TSV structure to cause reliability problems. In this study, the thermal stress in the TSV structure was measured by the wafer curvature method and its unique stress characteristics were compared to that of a Cu thin film structure. The thermo-mechanical characteristics of the Cu TSV structure were correlated to microstructure evolution during thermal cycling and the local plasticity in Cu in a triaxial stress state. These findings were confirmed by microstructure analysis of the Cu vias and finite element analysis (FEA) of the stress characteristics. In addition, the local plasticity and deformation in and around individual TSVs were measured by synchrotron x-ray microdiffraction to supplement the wafer curvature measurements. The importance and implication of the local plasticity and residual stress on TSV reliabilities are discussed for TSV extrusion and device keep-out zone (KOZ).Microelectronics Research Cente

High speed shadowgraphy for the study of liquid drops

The book contains invited lectures and selected contributions presented at the Enzo Levi and XVII Annual Meeting of the Fluid Dynamic Division of the Mexican Physical Society in 2011.This was work was sponsored by EPSRC grant number RG5560

Patterns of change in psychological variables leading up to competition in superior versus inferior performers

The study explored patterns of change in a number of potentially performance-related 27 variables (i.e., fatigue, social support, self-efficacy, autonomous motivation, mental skills) 28 during the lead up to a competitive triathlon, and whether these patterns of change differed 29 for relatively superior versus inferior performers. Forty-two triathletes completed an 30 inventory measuring the study variables every other day during a two-week period leading up 31 to competition. Performance was assessed using participants’ race time, and using a self-32 referenced relative score compared to personal best times. Multilevel growth curve analyses 33 revealed significant differences in growth trajectories over the two week period in mental 34 skills use, social support, and fatigue. The results provide novel insight into how athletes’ 35 fluctuating psychological state in the two weeks prior to competition may be crucial in 36 determining performance

Stress-Induced Delamination Of Through Silicon Via Structures

Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.Aerospace Engineerin

National income inequality predicts women's preferences for masculinized faces better than health does

This article is available open access through the publisher’s website at the link below. Copyright @ 2010 The Royal Society

13C-Methyl isocyanide as an NMR probe for cytochrome P450 active site

The cytochromes P450 (CYPs) play a central role in many biologically important oxidation reactions, including the metabolism of drugs and other xenobiotic compounds. Because they are often assayed as both drug targets and anti-targets, any tools that provide: (a) confirmation of active site binding and (b) structural data, would be of great utility, especially if data could be obtained in reasonably high throughput. To this end, we have developed an analog of the promiscuous heme ligand, cyanide,with a 13CH3-reporter attached. This 13C-methyl isocyanide ligand binds to bacterial (P450cam) and membrane-bound mammalian (CYP2B4) CYPs. It can be used in a rapid 1D experiment to identify binders, and provides a qualitative measure of structural changes in the active site

Thermomechanical Characterization And Modeling For TSV Structures

Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future technology requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper presents experimental measurements of the thermal stresses in TSV structures and analyses of interfacial reliability. The micro-Raman measurements were made to characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the precision wafer curvature technique was employed to measure the average stress and deformation in the TSV structures subject to thermal cycling. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias was analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. Furthermore, the impact of thermal stresses on interfacial reliability of TSV structures was investigated by a shear-lag cohesive zone model that predicts the critical temperatures and critical via diameters.Microelectronics Research Cente