A catalytic alloy approach for graphene on epitaxial SiC on silicon wafers

© Materials Research Society 2015. We introduce a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films. Using a Ni/Cu catalytic alloy, we obtain a transfer-free bilayer graphene directly on Si(100) wafers, at temperatures potentially compatible with conventional semiconductor processing. The graphene covers uniformly a 2″ silicon wafer, with a Raman ID/IG band ratio as low as 0.5, indicative of a low defectivity material. The sheet resistance of the graphene is as low as 25 Ω/square, and its adhesion energy to the underlying substrate is substantially higher than transferred graphene. This work opens the avenue for the true wafer-level fabrication of microdevices comprising graphene functional layers. Specifically, we suggest that exceptional conduction qualifies this graphene as a metal replacement for MEMS and advanced on-chip interconnects with ultimate scalability

Deep Level Defect Studies in MOCVD-Grown In(x)Ga(1-x)As(1-y)N(y) Films Lattice-Matched to GaAs

Deep level defects in MOCVD-grown, unintentionally doped p-type InGaAsN films lattice matched to GaAs were investigated using deep level transient spectroscopy (DLTS) measurements. As-grown p-InGaAsN showed broad DLTS spectra suggesting that there exists a broad distribution of defect states within the band-gap. Moreover, the trap densities exceeded 10{sup 15} cm{sup {minus}3}. Cross sectional transmission electron microscopy (TEM) measurements showed no evidence for threading dislocations within the TEM resolution limit of 10{sup 7} cm{sup {minus}2}. A set of samples was annealed after growth for 1800 seconds at 650 C to investigate the thermal stability of the traps. The DLTS spectra of the annealed samples simplified considerably, revealing three distinct hole trap levels with energy levels of 0.10 eV, 0.23 eV, and 0.48 eV above the valence band edge with trap concentrations of 3.5 x 10{sup 14} cm{sup {minus}3}, 3.8 x 10{sup 14} cm {sup {minus}3}, and 8.2 x 10{sup 14} cm{sup {minus}3}, respectively. Comparison of as-grown and annealed DLTS spectra showed that post-growth annealing effectively reduced the total trap concentration by an order of magnitude across the bandgap. However, the concentration of a trap with an energy level of 0.48 eV was not affected by annealing indicating a higher thermal stability for this trap as compared with the overall distribution of shallow and deep traps

S7N079-D536 c DEEP LEVEL DEFECT STUDIES IN MOCVD-GROWN [email protected] LATTICE-MATCHED TO GaAs

ABSTRACT Deep level defects in MOCVD-grown, unintentionally doped p-type InGaAsN films lattice matched to GaAs were investigated using deep level transient spectroscopy (DLTS) measurements. As-grown p-InGaAsN showed broad DLTS spectra suggesting that there exists a broad distribution of defect states within the band-gap. Moreover, the trap densities exceeded 10'5cm-3. Cross sectional transmission electron microscopy (TEM) measurements showed no evidence for threading dislocations within the TEM resolution limit of 107cm-z. A set of samples was annealed after growth for 1800 seconds at 650 'C to investigate the thermal stability of the traps. The DLTS spectra of the annealed samples simplified considerably, revealing three distinct hole trap levels with energy levels of 0.10 eV, 0.23 eV, and 0.48 eV above the valence band edge with trap concentrations of 3.5x10'4 cm-3,3.8x10'4 cm-3, and 8.2x10'4 cm-3, respectively. Comparison of as-grown and annealed DLTS spectra showed thatpost-growth annealing effectively reduced the total trap concentration by an order of magnitude across the bandgap. However, the concentration of a trap with an energy level of 0.48 eV was not affected by annealing indicating a higher thermal stability for this trap as compared with the overall distribution of shallow and deep traps

Self-aligned graphene on silicon substrates as ultimate metal replacement for nanodevices

We have pioneered a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from epitaxial 3C-SiC films [1,2]. The achievement of transfer-free bilayer graphene directly on silicon wafers, with high adhesion, at temperatures compatible with conventional semiconductor processing, and showing record- low sheet resistances, makes this approach an ideal route for metal replacement method for nanodevices with ultimate scalability fabricated at the wafer –level