MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented

A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model

This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor core for media processing applications. The core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. This paper presents an investigation of the feasibility of the core as a potential soft processing architecture for FPGA platforms. The core was synthesized on the entire Virtex FPGA family to evaluate its overall performance, scalability and portability. A special feature of the proposed architecture is its simple programming model which allows low level programming. Throughput results for popular benchmarks coded using the programming model and cycle accurate simulator are presented

A C++-embedded Domain-Specific Language for programming the MORA soft processor array

MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM). We present a Domain-Specific Language (DSL) for high-level programming of the MORA soft processor array. The DSL is embedded in C++, providing designers with a familiar language framework and the ability to compile designs using a standard compiler for functional testing before generating the FPGA bitstream using the MORA toolchain. The paper discusses the MORA-C++ DSL and the compilation route into the assembly for the MORA machine and provides examples to illustrate the programming model and performance

Towards a Theory of Practice: Critical Transdisciplinary Multiliteracies

About the book: Education institutions and organizations throughout the world are currently being held accountable for achieving and maintaining historically unmatched standards of academic quality and performance. Accreditation bodies; policy makers; boards of trustees; and teacher, parent, and student groups all place educational institutions and organizations under unprecedented accountability pressures. The aim of this volume is to explore and better understand how these pressures are impacting a broad range of social and cultural issues and, subsequently, how these issues impact student motivation and learnin

On q-Laplace Transforms of the q-Bessel Functions

Mathematics Subject Classification: 33D15, 44A10, 44A20The present paper deals with the evaluation of the q-Laplace transforms of a product of basic analogues of the Bessel functions. As applications, several useful special cases have been deduced

On the Design and Analysis of Parallel and Distributed Algorithms

Arrival of multicore systems has enforced a new scenario in computing, the parallel and distributed algorithms are fast replacing the older sequential algorithms, with many challenges of these techniques. The distributed algorithms provide distributed processing using distributed file systems and processing units, while network is modeled as minimum cost spanning tree. On the other hand, the parallel processing chooses different language platforms, data parallel vs. parallel programming, and GPUs. Processing units, memory elements and storage are connected through dynamic distributed networks in the form of spanning trees. The article presents foundational algorithms, analysis, and efficiency considerations.Comment: 9 page

On the D0D^0 -- DsD_s lifetime difference and τ→7π+ντ\tau\to 7\pi + \nu_\tau decays

In this paper we discuss some aspects of inclusive decays of charmed mesons and also decays of the $\tau$ lepton into $\nu_\tau + 7\pi$. We find that phase space effects are likely to explain the observed lifetime ratio $\tau(D_s^+) / \tau(D^0)$ = 1.17. In particular one need not appeal to a large annihilation contribution in the inclusive $D^0$ decay which, being absent in $D_s^+$ decays could also contribute to the enhanced $D^0$ decay rate relative to that of the $D_s^+$. Examining a separate problem, we find that the rate for $\tau\to \nu_\tau + 7\pi$ is almost completely dominated by the tiny phase space for the final eight particle state. Using an effective chiral Lagrangian to estimate the matrix element yields a branching ratio into the channel of interest far smaller than the present upper bound.Comment: No figure