Influence of synthesis conditions on properties of green-reduced graphene oxide

[EN] Green reduction of graphene oxide (GO) was performed using ascorbic acid (AA) in the presence of poly(sodium 4-styrenesulfonate), which resulted in reduced graphene oxide (PSS-rGO) with excellent solubility and stability in water. Large rGO sheets of 4 mu m(2) area and 1.1-nm thickness were obtained. The measurements showed that noncovalent functionalization with PSS molecules prevented rGO from aggregation. The parameters of graphite oxidation process and AA: GO w/w ratio were evaluated, and the obtained results showed that the properties of the reduced material (PSS-rGO) can be tailored by proper selection and adjustment of these parameters.The authors thank the European Commission for their financial support through the project no. NMP3-SL-2010-246073.Pruna, A.; Pullini, D.; Busquets, D. (2013). Influence of synthesis conditions on properties of green-reduced graphene oxide. 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Renormalization of Coulomb interactions in s-wave superconductor Nax_xCoO2_2

We study the renormalized Coulomb interactions due to retardation effect in Na$_x$CoO$_2$. Although the Morel-Anderson's pseudo potential for $a_{1g}$ orbital $\mu^*_{a1g}$ is relatively large because the direct Coulomb repulsion $U$ is large, that for interband transition between $a_{1g}$ and $e_g'$ orbitals $\mu^*_{a1g,eg'}$ is very small since the renormalization factor for pair hopping $J$ is square of that for $U$. Therefore, the s-wave superconductivity due to valence-band Suhl-Kondo mechanism will survive against strong Coulomb interactions. The interband hopping of Cooper pairs due to shear phonons is essential to understand the superconductivity in Na$_x$CoO$_2$.Comment: 2pages, 2figures, Proceedings of ICM in Kyoto, 200

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

This paper presents Mr. Wolf, a parallel ultra-low power (PULP) system on chip (SoC) featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals. The small core can offload compute-intensive kernels to an eight-core floating-point capable of processing engine available on demand. The proposed SoC, implemented in a 40-nm LP CMOS technology, features a 108-mu W fully retentive memory (512 kB). The IO subsystem is capable of transferring up to 1.6 Gbit/s from external devices to the memory in less than 2.5 mW. The eight-core compute cluster achieves a peak performance of 850 million of 32-bit integer multiply and accumulate per second (MMAC/s) and 500 million of 32-bit floating-point multiply and accumulate per second (MFMAC/s) -1 GFlop/s-with an energy efficiency up to 15 MMAC/s/mW and 9 MFMAC/s/mW. These building blocks are supported by aggressive on-chip power conversion and management, enabling energy-proportional heterogeneous computing for always-on IoT end nodes improving performance by several orders of magnitude with respect to traditional single-core MCUs within a power envelope of 153 mW. We demonstrated the capabilities of the proposed SoC on a wide set of near-sensor processing kernels showing that Mr. Wolf can deliver performance up to 16.4 GOp/s with energy efficiency up to 274 MOp/s/mW on real-life applications, paving the way for always-on data analytics on high-bandwidth sensors at the edge of the Internet of Things

Influence of Deposition Potential on Structure of ZnO Nanowires Synthesized in Track-Etched Membranes

Single-crystal ZnO nanowires long up to several microns were fabricated by one-step electrochemical deposition. A template-based process employing track-etched polycarbonate (TE-PC) membranes was used for this purpose. The morphology and the structure characteristics of the ZnO nanowires were analyzed by means of Scanning Electron Microscopy (SEM), Focused Ion Beam (FIB), Transmission Electron Microscopy (TEM), and Selected Area Electron Diffraction (SAED). The growth process conditions turned out to have a marked influence on the crystal nature and morphology of the nanowires. Deposition rates ranging from 0.4 nm s -1 and up to 0.6 nm s -1 were recorded for the growth of ZnO nanowires. The obtained results showed that by using carefully controlled deposition conditions single crystalline nanowires and fine-grained structures can be routinely obtained. © 2012 The Electrochemical Society.This work was supported by the European Commission through the program PEOPLE, by the project no. MRTN-CT-2006-035884.Pruna, AI.; Pullini, D.; Busquets Mataix, DJ. (2012). Influence of Deposition Potential on Structure of ZnO Nanowires Synthesized in Track-Etched Membranes. Journal of The Electrochemical Society. 159(4):92-98. doi:10.1149/2.003205jesS9298159

High-Efficiency Electrodeposition of Large Scale ZnO Nanorod Arrays for Thin Transparent Electrodes

In the present work an effective technique to synthesize large-scale c-axis oriented ZnO nanorod (NR) arrays is presented. The manuscript reports a single-step cathodic electrodeposition, either in aqueous and organic electrolytes, to fill up ultra-thin anodic nanoporous alumina templates. Prior to growing, self-ordered hexagonal array of cylindrical nanopores have been fabricated by anodizing Al thin films previously deposited onto ITOglass substrates. The diameter and the aspect ratio of the vertically aligned nanopores are about 60 nm and 8:1, respectively. The results of this work demonstrate that using dimethyl sulfoxide (DMSO) as an electrolyte leads to a growth more homogeneous in shape and crystallinity, and with 60 deposition efficiency - the highest by now in literature. This fact is most probably due to a better infiltration of the alumina nanopores by this electrolyte. SEM and XRD analysis were employed for the study of morphology and crystalline structure of the obtained ZnO NR. These measurements showed furthermore that ZnO nanorod arrays are uniformly embedded into the hexagonally ordered nanopores of the anodic alumina membrane. DMSO proved to be an optimal electrolyte to obtain single-crystalline ZnO NR arrays, highly transparent in visible light range (80 transmittance). © 2011 The Electrochemical Society.The authors thank for the financial support by the European Commission, DG Research through the program PEOPLE, by the project no. MRTN-CT-2006-035884.Pullini, D.; Pruna, AI.; Zanin, S.; Busquets Mataix, DJ. (2012). High-Efficiency Electrodeposition of Large Scale ZnO Nanorod Arrays for Thin Transparent Electrodes. Journal of The Electrochemical Society. 159(2):45-51. doi:10.1149/2.093202jesS4551159

Nanoporous PBI Membranes by Track-Etching for High Temperature PEMFC

This article describes for the first time the preparation of conducting track-etched PBI membranes 25 mm thick with pore diameter values varying from 15 nm to 50 nm and overall porosity up to 10%. The TGA, DSC and FTIR characterization results for the so obtained nanoporous membranes reveal the chemical modification of PBI upon irradiation along the track walls. A clear conduction outperforming is shown by phosphoric acid doped track-etched PBI in comparison with dense PBI counterparts. This behavior could be explained by the effective contribution of additional pathways for proton transport involving shorter benzimidazole fragments, cross-linked PBI nanodomains and free amphoteric phosphoric acid molecules settled on the pore walls

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper