Finite Element Analysis of Beam with Smart Materials

Impedance-based structural health-monitoring techniques are developed by utilizing a number of smart material technologies and represent a new non-destructive evaluation (NDE) method. The basic concept of this approach is monitoring the variations in mechanical impedance of the structure resulted by the presence of damage. Since it is very difficult to measure the structural mechanical-impedance, the new impedance methods utilize the electromechanical coupling properties of piezoelectric materials. The impedance-based structural health monitoring is done by using piezoelectric patches which are bonded to the host structure that act as both sensors and actuators on the system. When a PZT comes under a change in environment, it produces an electric charge. Conversely when an electric field is applied the PZT undergoes a mechanical strain. A sinusoidal voltage is used for the excitation of the PZT patch. As the patch is surface bonded to the host structure, the structure deforms along with it and gives a local dynamic response to the vibration. That response is then transmitted back from the PZT patch as an electrical response. The electrical response is then analysed where damage is shown as a phase shift or magnitude change in the impedance. In this project finite element simulation of the interaction between a PZT patch and a structure utilizing the electromechanical impedance (EMI) technique is studied. Simulation of the host structure with a piezoelectric patch at a high frequency range (up to 1000 kHz) using ANSYS version 13, was successfully performed. Advantages over the traditional FEA based impedance model and the impedance based analytical models include higher accuracy, direct acquisition of electrical admittance/impedance. This study proves that the FEM could emerge as an excellent alternative to structural health monitoring by visual inspection method

Distributed task offloading in a multi-tier cloud infrastructure

With the advent of edge computing, computational servers were brought closer to end devices to reduce the latency of offloading tasks. This has led to a sharp rise in the number of mobile-edge applications. Due to the heterogeneous requirements of such applications, efficient resource management in an edge infrastructure is a challenging problem. In this study, we propose a distributed task offloading algorithm for a multitier cloud infrastructure. The algorithm involves a search routine that uses Ant Colony Optimization (ACO) to search for the optimal solution, and a consensus routine for all the hosts to converge on the best solution. An asynchronous distributed environment was to evaluate and compare its performance with its centralized counterpart. Results show the effectiveness of the distributed algorithm in reducing the computational complexity without compromising on the optimality of the solution. The proposed algorithm could help scale the modern cloud/edge infrastructure to cater to the rising number of services.Bachelor of Engineering (Computer Science

Implementation of Full Adder at One Terabyteper Second Speed Using Cadence

In digital circuits design high speed, high throughput and small silicon area and at the same time low power consumption of digital circuit is most important parameter for digital circuit designers. Most of the VLSI applications, such as image and video processing, digital signal processing and microprocessors extensively use arithmetic operations. Addition, subtraction, multiplication and accumulate are most commonly used operations. Adders are some of the most critical data path circuits requiring considerable design effort in order to squeeze out as much performance gain as possible. Various adder structures can be used to execute addition such as serial and parallel structures and most of researches have done research on the design of high-speed, low-area, or low-power adders. Adders like carry select adder, carry look ahead adder, carry skip adder, carry save adder etc exist numerous adder implementations each with good attributes.The main objective of this thesis is implementation of full adder at one Terabyte per second speed. The simulation is done using Cadence and we have recorded the performance in propagating implementation of full adder at one terabyte per second. This thesis focuses on the implementation and simulation of 4 bit carry look-ahead adder, carry skip adder and carry select adder based on synthesis analysis and compared for their performance. Especially, this work focuses on the reduction of the power dissipation and implements high performance