Method and apparatus for determining IDDQ

A test apparatus for testing a device under test (DUT) to detect a defect comprises a measurement circuit (ME), a threshold circuit (TH), and a control circuit (CG). The measurement circuit (ME) comprises a counter (C 1 ) which counts clock pulses (OLK) during a count period (TC) to obtain a counted number (N) of clock pulses (CLK). The count period (TC) has a start determined by the start (tl) of a testing cycle which occurs at the instant a switch (S) which is coupled to an terminal (IN) of the device under test (DUT) removes a power supply voltage (VDD) from the terminal (IN) and the voltage (VDD') at the terminal (IN) starts decaying. An end of the count period (TC) is determined by an instant (t 2 ) a comparator (COM 1 ) detects that the voltage (VDD') at the terminal (IN) crosses a reference value (VREF).; The control circuit (CG) generates the clock signal (CLK) and/or a reference number (NTH) taking into account the variability of the manufacturing process of the circuit under test (CUT). The threshold circuit (TH) generates a pass/fail signal (PF) by comparing the counted number (N) and the reference number (NTH)

Circuit and method for controlling the threshold voltage of transistors.

A control unit, for controlling a threshold voltage of a circuit unit having transistor devices, includes a reference circuit and a measuring unit. The measuring unit is configured to measure a threshold voltage of at least one sensing transistor of the circuit unit, and to measure a threshold voltage of at least one reference transistor of the reference circuit. A differential voltage generator is configured to generate a differential voltage from outputs of the measuring unit and a bulk connection of the transistor devices in the circuit unit to which the differential voltage is fed as a biasing voltage

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Mound defect modeling in yield forecasts

Although the majority of defects found in manufacturing lines have predominantly two-dimensional effects, there are many situations in which 2-D defect models do not suffice, e.g., tall layer bulks, residual resist flakes, and extraneous materials embedded in the IC. In this paper a more general model based on mound defects is presented. Both catastrophic and soft effects of mound defects are investigated. The defect model is based on the geometrical properties that result from the interaction between IC and defect size in two coordinate spaces: x-y and z. The approach to model catastrophic effects is a natural extension to the concept of critical areas, namely, the extraction of critical volumes. The simplicity of the extraction method makes it suitable for inclusion in common layout editing tools. Through the course of this work hints to the origins of mound defects will be given, conditions to capture critical volumes will be developed, realistic layout results will be shown, and a yield model taking into account these new kind of defects will be presente

BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits

6 páginas, 10 figuras.This paper reports a new built-in self-test scheme for analog and mixed-signal devices based on die-level process monitoring. The objective of this test is not to replace traditional specification-based tests, but to provide a reliable method for early identification of excessive process parameter variations in production tests that allows quickly discarding of the faulty circuits. Additionally, the possibility of on-chip process deviation monitoring provides valuable information, which is used to guide the test and to allow the estimation of selected performance figures. The information obtained through guiding and monitoring process variations is re-used and supplement the circuit calibration.Peer reviewe

Functional testing for cellular neural networks

A novel approach to test the functional behaviour of cellular neural networks (CNNs) is proposed. The method attains 100% stuck-at fault coverage regardless of the array size without any extra hardware for its implementation. The Letter discusses the new fault model, presents the algorithmic procedures and shows simulated testing results

Built-in current sensor for ΔIDDQ testing

This paper presents the implementation of a built-in current sensor for ¿IDDQ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) enabling versatile testing strategy through the implementation of two advanced ¿IDDQ testing algorithms. The monitor has been manufactured in a 0.18-µm CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 µA for a background current less than 100 µA or 1% of background currents over 100 µA to a total of 1-mA full scale. The sensor operates at a maximum clock speed of 250 MHz. The quiescent current is indirectly determined by counting a number of clock pulses which occur during the time the voltage at the disconnected node drops below a reference voltage value. Basically, at the end of the count period, the counted value is inversely proportional to the quiescent current of the device under test. Then, a ¿IDDQ unit processes the counted number and the outcome is compared with a reference number to determine whether a defect exists in the device under test. Accuracy is improved by adjusting the value of the reference number and the frequency of the clock signal depending upon the particular process corner of the circuit under test. The monitor has been verified in a test chip consisting of one DSP-like circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits

Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (Ioff) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (¿Vto) has a two-sided effect on the off-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the Vt mismatch shift. This effect can be so severe that Ioff can increase by more than one order of magnitude with respect to its nominal value due only to Vto mismatch. We further show through experimental results that the Vto mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same Ioff level as for a Vto mismatch characterized out of the subthreshold regime

Filtering and spectral processing of 1-D signals using cellular neural networks

This paper presents cellular neural networks (CNN) for one-dimensional discrete signal processing. Although CNN has been extensively used in image processing applications, little has been done for 1-dimensional signal processing. We propose a novel CNN architecture to carry out these tasks. This architecture consists of a shift register, e.g., a charge coupled device, and a 1×n neural array. Each cell processes a sample of the input signal. By using appropriate templates and shifting the input signal the CNN array is capable of performing FIR filtering, discrete Fourier transform, and wavelet decomposition and reconstruction. Even though this implementation is not more efficient than conventional methods, the paper shows that an analog computer based on the CNN paradigm can also be used to perform the linear operations described above. Simulation results and comparisons for spectral audio applications are presente