1,323 research outputs found

    Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation

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    This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 µm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement application

    Injury History in the Collegiate Equestrian Athlete: Part I: Mechanism of Injury, Demographic Data and Spinal Injury

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    ABSTRACT Purpose: Equestrian sports are known to have a high risk and rate of injury. While there is injury data available on acute injuries in the equestrian population, it is of a general nature. Within that data appears to be a lack of information on the collegiate equestrian athlete. Thus, the purpose of the current study and this analysis is to describe the demographics and incidence of spinal injuries found in intercollegiate equestrian athlete. Method: A survey was developed with input from each author and implemented in Mach forms. It was sent to 43 equestrian coaches in the Eastern United States who passed it on to their athletes. We estimated 753 athletes would have access to the survey and had a total of 73 respondents. Descriptive statistics were calculated for total number of injuries for each injury category. Results: Demographic information, conditioning activity, riding style, pain medication use, total responses (injuries) per body area and injuries to the spine and pelvis are detailed in tables 1-6. Of interesting note is only 73% of respondents reported having access to or utilizing the schools athletic program as part of their participation on the schools equestrian team. Conclusions and Recommendations: The current study is amongst the first, if not the first, to report specifically on injury patterns and frequency in US collegiate equestrian athletes. There were several findings that from a sports medicine and athletic perspective are concerning. The lack of overall knowledge and research about the equestrian athlete would appear to put it in the same position as cheerleading was 20 years ago. Significantly more sport specific research is needed to improve the health and safety of the athlete

    Injury History in the Collegiate Equestrian Athlete: Part II: Head, Upper and Lower Extremities

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    ABSTRACT Purpose: Equestrian sports are known to have a high risk and rate of injury. While there is injury data available on acute injuries in the equestrian population, it is of a general nature. Within that data appears to be a lack of information on the collegiate equestrian athlete. Thus, the purpose of the current study and this analysis is to describe the incidence of upper and lower extremity injuries and head injuries, sans concussion, in intercollegiate equestrian athlete. Method: A survey was developed with input from each author and implemented in Mach forms. It was sent to 43 equestrian coaches in the Eastern United States who passed it on to their athletes. We estimated 753 athletes would have access to the survey and had a total of 73 respondents. Descriptive statistics were calculated for total number of injuries for each injury category. Results: Detailed injury information on the upper and lower extremity and head is found in tables 1-10. The upper and lower extremity and head accounted for 15.97, 60.35 and 4.33 percent respectively of the injuries in this group of athletes.Conclusions and Recommendations:The current study is amongst the first, if not the first, to report specifically on injury patterns and frequency in US collegiate equestrian athletes. The data indicate that there is an extremely high incidence of injury in the collegiate equestrian population. The lower extremity is particularly susceptible to injury in the equestrian athletes. The lack of data available in a sport, which can be classified as collision and has the potential for significant, long-standing disability from an early age due to interaction with the horse, is troubling. Significantly more sport specific research is needed to improve the health and safety of these athletes

    Reconfigurable logic for hardware IP protection: Opportunities and challenges

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    Protecting the intellectual property (IP) of integrated circuit (IC) design is becoming a significant concern of fab-less semiconductor design houses. Malicious actors can access the chip design at any stage, reverse engineer the functionality, and create illegal copies. On the one hand, defenders are crafting more and more solutions to hide the critical portions of the circuit. On the other hand, attackers are designing more and more powerful tools to extract useful information from the design and reverse engineer the functionality, especially when they can get access to working chips. In this context, the use of custom reconfigurable fabrics has recently been investigated for hardware IP protection. This paper will discuss recent trends in hardware obfuscation with embedded FPGAs, focusing also on the open challenges that must be necessarily addressed for making this solution viable

    Optimizing the Use of Behavioral Locking for High-Level Synthesis

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    The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and IP theft. Logic locking is a promising solution, but there are many open concerns. First, even when applied at a higher level of abstraction, locking may result in significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a meta-framework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chip’s specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. Our meta-framework supports different strategies to explore the design space and to select points to be locked automatically. We evaluated our method on the optimization of differential entropy, achieving better results than random or topological locking: 1) we always identify a valid solution that optimizes the security metric, while topological and random locking can generate unfeasible solutions; 2) we minimize the number of bits used for locking up to more than 90% (requiring smaller tamper-proof memories); 3) we make better use of hardware resources since we obtain similar overheads but with higher security metric
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