Carleman estimate for infinite cylindrical quantum domains and application to inverse problems

We consider the inverse problem of determining the time independent scalar potential of the dynamic Schrödinger equation in an infinite cylindrical domain, from one Neumann boundary observation of the solution. Assuming that this potential is known outside some fixed compact subset of the waveguide, we prove that it may be Lipschitz stably retrieved by choosing the Dirichlet boundary condition of the system suitably. Since the proof is by means of a global Carleman estimate designed specifically for the Schrödinger operator acting in an unbounded cylindrical domain, the Neumann data is measured on an infinitely extended subboundary of the cylinder

Sharp Rejection Techniques in High Frequency Active-RC LPF for UWB Applications

This paper describes a sharp-rejection technique in designing active-RC LPF for MB-OFDM UWB applications. Sharp rejection is attributed to the combination of different AC characteristic of three Biquads in series. A simple operational amplifier (Op-amp) is adopted to ensure high frequency and high linear performance for the designed filter. The cutoff frequency is 264MHz, with 13dB rejection at 290MHz and about 50dB at twice bandwith. the LPF is designed in 0.13um IBM CMOS process with pass-band ripple of less that 1dB, IIP3 is 23dBm while cnsuming 8.4mA from 1.5V supply

Sharp Rejection Techniques in High Frequency Active-RC LPF for UWB Applications

This paper describes a sharp-rejection technique in designing active-RC LPF for MB-OFDM UWB applications. Sharp rejection is attributed to the combination of different AC characteristic of three Biquads in series. A simple operational amplifier (Op-amp) is adopted to ensure high frequency and high linear performance for the designed filter. The cutoff frequency is 264MHz, with 13dB rejection at 290MHz and about 50dB at twice bandwith. the LPF is designed in 0.13um IBM CMOS process with pass-band ripple of less that 1dB, IIP3 is 23dBm while cnsuming 8.4mA from 1.5V supply

9.1 dBm IIP3 36 dB Gain Controllable LNA for WCDMA in 0.13-m CMOS

This article presents a low-power, high-linearity cascodetype low noise amplifier (LNA) with 36 dB of variable gain for the WIDE Code Division Multiple Access systems. By enhancing the substrate resistance of a common gate transistor along with adopting multiple-gate technique, the linearity is significantly improved. Shunt-current steering is adopted for smooth gain control. Step gain mode is used to further increase the gain control range. The main common source transistor is disabled in attenuation mode, saving unwanted power consumption. Measurements show maximum gain of 12.3 dB with S11 of 19.5 dB, and S22 of 14 dB. The total gain control range is 36 dB. NF is measured as 2 dB and two-tone test shows 9.1 dBm of IIP3. Implemented in 0.13-m CMOS technology, the LNA consumes only 1.6 mA at maximum gain mode and only 0.2 mA in attenuation mode from 1.2 V supply. Its die size is 0.3 mm2. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1385–1388, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop. 2432

Model Counting Modulo Theories

PhD finalThis thesis is concerned with the quantitative assessment of security in software. More specifically, it tackles the problem of efficient computation of channel capacity, the maximum amount of confidential information leaked by software, measured in Shannon entropy or R²nyi's min-entropy. Most approaches to computing channel capacity are either efficient and return only (possibly very loose) upper bounds, or alternatively are inefficient but precise; few target realistic programs. In this thesis, we present a novel approach to the problem by reducing it to a model counting problem on first-order logic, which we name Model Counting Modulo Theories or #SMT for brevity. For quantitative security, our contribution is twofold. First, on the theoretical side we establish the connections between measuring confidentiality leaks and fundamental verification algorithms like Symbolic Execution, SMT solvers and DPLL. Second, exploiting these connections, we develop novel #SMT-based techniques to compute channel capacity, which achieve both accuracy and efficiency. These techniques are scalable to real-world programs, and illustrative case studies include C programs from Linux kernel, a Java program from a European project and anonymity protocols. For formal verification, our contribution is also twofold. First, we introduce and study a new research problem, namely #SMT, which has other potential applications beyond computing channel capacity, such as returning multiple-counterexamples for Bounded Model Checking or automated test generation. Second, we propose an alternative approach for Bounded Model Checking using classical Symbolic Execution, which can be parallelised to leverage modern multi-core and distributed architecture. For software engineering, our first contribution is to demonstrate the correspondence between the algorithm of Symbolic Execution and the DPLL(T ) algorithm used in state-of-the-art SMT solvers. This correspondence could be leveraged to improve Symbolic Execution for automated test generation. Finally, we show the relation between computing channel capacity and reliability analysis in software.School of Electronic Engineering and Computer Science scholarshi

380 MHz Low-Power Sharp-Rejection Active-RC LPF for IEEE 802.15.4a UWB WPAN

This paper describes a wide-band sharp-rejection active-RC low pass filter (LPF) for pulse-based UWB IEEE 802.15.4a WPA, applications. Sharp rejection is attributed to the combination of different AC characteristic of three biquads in series. A simple operational amplifier (Op-amp) is adopted to ensure high frequency performance for the designed filter. The LPF is designed in 0.13μm TSMC CMOS process. The cutoff frequency is 380MHz with about 50% of the tuning range from 300-500MHz. The rejection is 40 dB at 600 MHz. The passband ripple is less than 1.5dB and the filter consumes 4.6mA from 1.2V supply. Core chip size is 580 x 700μm2