Polyimide (PI) films by chemical vapor deposition (CVD): Novel design, experiments and characterization

Polyimide (PI) has been deposited by chemical vapor deposition (CVD) under vacuum over the past 20 years. In the early nineties, studies, experiences and characterization were mostly studied as depositions from the co-evaporation of the dianhydride and diamine monomers. Later on, several studies about its different applications due to its interesting mechanical and electrical properties enhanced its development. Nowadays, not many researches around PI deposition are being carried. This paper presents a PI film deposition research project with an original CVD process design. The deposition is performed under ambient conditions (atmospheric pressure) through a gas flux vector. Design of apparatus, deposition conditions and preliminary characterizations (IR, SEM and surface analyses) are discussed

TLC y género. ¿Una relación armónica?

El tema de género y comercio ha estado permanentemente ausente en las estadísticas oficiales, en el debate público, en los centros académicos y de estudio, y en distintas instancias institucionales. Nos referimos tanto a los impactos potenciales en las vidas de las mujeres de las negociaciones comerciales internacionales. Para comenzar este análisis, nos situaremos en el espacio geográfico desde el cual estamos hablando, y su relación con la apertura económica que se ha venido impulsando desde hace tres décadas. Más allá de cualquier mitificación al respecto, podemos señalar que la estrategia de crecimiento del modelo chileno ha tenido profundas consecuencias en distintas áreas de la vida económica, social y cultural del país

The use of soft lithography to reproduce snail-like movement by creating pressure gradients in thin films

Thesis (S.B.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2004.Includes bibliographical references (p. 18-20).By imitating nature, man finds ways to expand his capacities. To achieve this aim, he often takes natures designs, simplifies them to their most basic principles and then works in a retrograde fashion to add back the complexity originally stripped away to make the first discoveries. This thesis is based on previous work done on modeling snail movement on a macroscopic scale using a motor driven wave propagation machine. This project scaled down the mechanism to a size more commonly found in nature. This downscaling required a new method for producing waves. Peristaltic pumping achieved through the use of soft-lithography and pneumatics was the method chosen. This combination of ideas proved challenging for several reasons. First, the pumping method had previously only been used with one channel per pneumatic input, whereas the snail required each input to feed a multitude of branching channels creating a more complicated fluid dynamics problem. Second, the snail waves were downscaled from a continuous sinusoid to the three phase stepping mechanism of the peristaltic pump. Each three-phase cycle was considered equivalent to one wavelength. Thus, after creating a design that could move, the ratio between the traveling wavelength speed and subsequent net movement were compared to the aforementioned mathematical model. The model's ratio was 0.56 net/wave velocity. The actual ratio was .05 net/wave velocity. The difference by an order of magnitude could be attributed to the discontinuity of the pumping mechanism as opposed to the continuous nature of an actual traveling wave.by Pey-Hua B. Hwang.S.B

Instruction fetch architectures and code layout optimizations

The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing a higher performance processor implies balancing all the pipeline stages to ensure that overall performance is not dominated by any of them. This means that a faster execution engine also requires a faster fetch engine, to ensure that it is possible to read and decode enough instructions to keep the pipeline full and the functional units busy. This paper explores the challenges faced by the instruction fetch stage for a variety of processor designs, from early pipelined processors, to the more aggressive wide issue superscalars. We describe the different fetch engines proposed in the literature, the performance issues involved, and some of the proposed improvements. We also show how compiler techniques that optimize the layout of the code in memory can be used to improve the fetch performance of the different engines described Overall, we show how instruction fetch has evolved from fetching one instruction every few cycles, to fetching one instruction per cycle, to fetching a full basic block per cycle, to several basic blocks per cycle: the evolution of the mechanism surrounding the instruction cache, and the different compiler optimizations used to better employ these mechanisms.Peer ReviewedPostprint (published version

Automated construction and analysis of political networks via open government and media sources

We present a tool to generate real world political networks from user provided lists of politicians and news sites. Additional output includes visualizations, interactive tools and maps that allow a user to better understand the politicians and their surrounding environments as portrayed by the media. As a case study, we construct a comprehensive list of current Texas politicians, select news sites that convey a spectrum of political viewpoints covering Texas politics, and examine the results. We propose a ”Combined” co-occurrence distance metric to better reflect the relationship between two entities. A topic modeling technique is also proposed as a novel, automated way of labeling communities that exist within a politician’s ”extended” network.Peer ReviewedPostprint (author's final draft

Software trace cache

We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details of the processor/architecture in order to increase fetch performance. The Software Trace Cache (STC) is a code layout algorithm with a broader target than previous layout optimizations. We target not only an improvement in the instruction cache hit rate, but also an increase in the effective fetch width of the fetch engine. The STC algorithm organizes basic blocks into chains trying to make sequentially executed basic blocks reside in consecutive memory positions, then maps the basic block chains in memory to minimize conflict misses in the important sections of the program. We evaluate and analyze in detail the impact of the STC, and code layout optimizations in general, on the three main aspects of fetch performance; the instruction cache hit rate, the effective fetch width, and the branch prediction accuracy. Our results show that layout optimized, codes have some special characteristics that make them more amenable for high-performance instruction fetch. They have a very high rate of not-taken branches and execute long chains of sequential instructions; also, they make very effective use of instruction cache lines, mapping only useful instructions which will execute close in time, increasing both spatial and temporal locality.Peer ReviewedPostprint (published version