Metal-catalyst-free growth of silica nanowires and carbon nanotubes using Ge nanostructures

The use of Ge nanostructures is investigated for the metal-catalyst-free growth of silica nanowires and carbon nanotubes (CNTs). Silica nanowires with diameters of 10-50 nm and lengths of ? 1 ?m were grown from SiGe islands, Ge dots, and Ge nanoparticles. High-resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDS) reveal that the nanowires grow from oxide nanoparticles on the sample surface. We propose that the growth mechanism is thermal diffusion of oxide through the GeO2 nanostructures. CNTs with diameters 0.6-2.5 nm and lengths of less than a few ?m were similarly grown by chemical vapor deposition from different types of Ge nanostructures. Raman measurements show the presence of radial breathing mode peaks and the absence of the disorder induced D-band, indicating single walled CNTs with a low defect density. HRTEM images reveal that the CNTs also grow from oxide nanoparticles, comprising a mixture of GeO2 and SiO2

Growth of Carbon Nanotubes on HfO2 towards Highly Sensitive Nano-Sensors

Carbon nanotube (CNT) growth on HfO2 is reported for the first time. The process uses a combination of Ge and Fe nanoparticles and achieves an increase in CNT density from 0.15 to 6.2 mm length/mm2 compared with Fe nanoparticles alone. The synthesized CNTs are assessed by the fabrication of back-gate CNT field-effect transistors with Al source/drain contacts for nano-sensor applications. The devices exhibit excellent p-type behavior with an Ion=Ioff ratio of 105 and a steep sub-threshold slope of 130 mV/dec

Depletion-Isolation Effect in Vertical MOSFETs During the Transition From Partial to Fully Depleted Operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling

Leakage Current Mechanisms in SiGe HBTs Fabricated Using Selective and Nonselective Epitaxy

SiGe heterojunction bipolar transistors (HTBs) have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by nonselective epitaxy for the p+ SiGe base and n-Si emitter cap. DC electrical characteristics are compared with cross-section TEM images to identify the mechanisms and origins of leakage currents associated with the epitaxy in two different types of transistor . In the first type, the polysilicon emitter is smaller than the collector active area, so that the extrinsic base implant penetrates into the single-crystal Si and SiGe around the perimeter of the emitter and the polycrystalline Si and SiGe exrtrinsic base. In these transistors, the Bummel plots are near-ideal and there is no evidence of emitter/collector leakage. In the second type, the collector active area is smaller than the polysilicon emitter, so the extrinsic base implant only penetrates into the polysilicon extrinsic base. In these transistors, the leakage currents observed depend on the base doping level. In transistors with a low doped base, emitter/collector and emitter/base leakage is observed, whereas in transistors with a high doped base only emitter/base leakage is observed. The emitter/collector leakage is explained by punch through o fhte base caused by thinning of the SiGe base at the emitter perimeter. The emitter/base leakeage is shown to be due to Poole-Frenkel mechanism and is explained by penetration of the emitter/base depletion region into the p+ polysilicon extrinsic base at the emitter periphery. Variable collector/base reverse leakage currents are observed and a variety of mechanisms are observed, including Shockley-Read-Hall recombination, trap assisted tunneling, Poole Frenkel and band to band tunneling. These result s are explained by the presence of polysilicon grains on the sidewalls of the field oxide at the collector perimeter

Properties and benefits of fluorine in silicon and silicon-germanium devices, Journal of Telecommunications and Information Technology, 2007, nr 2

This paper reviews the behaviour of fluorine in silicon and silicon-germanium devices. Fluorine is shown to have many beneficial effects in polysilicon emitter bipolar transistors, including higher values of gain, lower emitter resistance, lower 1/f noise and more ideal base characteristics. These results are explained by passivation of trapping states at the polysilicon/silicon interface and accelerated break-up of the interfacial oxide layer. Fluorine is also shown to be extremely effective at suppressing the diffusion of boron, completely suppressing boron transient enhanced diffusion and significantly reducing boron thermal diffusion. The boron thermal diffusion suppression correlates with the appearance of a fluorine peak on the SIMS profile at approximately half the projected range of the fluorine implant, which is attributed to vacancy- fluorine clusters. When applied to bipolar technology, fluorine implantation leads to a record fT of 110 GHz in a silicon bipolar transistor

Charge-pumping characterization of FILOX vertical MOSFETs, Journal of Telecommunications and Information Technology, 2007, nr 3

This paper presents for the first time the results of charge-pumping (CP) measurements of FILOX vertical transistors. The aim of these measurements is to provide information on the density of interface traps at the Si-SiO2 interface fabricated in a non-standard process. Flat-band and threshold voltage, as well as density of interface traps are determined. Good agreement between threshold-voltage values obtained from CP and I-V measurements is observed

Recent developments in vertical MOSFETs and SiGe HBTs, Journal of Telecommunications and Information Technology, 2004, nr 1

There is a well recognised need to introduce new materials and device architectures to Si technology to achieve the objectives set by the international roadmap. This paper summarises our work in two areas: vertical MOSFETs, which can allow increased current drive per unit area of Si chip and SiGe HBT's in silicon-on-insulator technology, which bring together and promise to extend the very high frequency performance of SiGe HBT's with SOI-CMOS