Binary Sequence Detector-Patent

Binary sequence detector with few memory elements and minimized logic circuit complexit

Minimal hardware, binary sequence pseudonoise generator and detector

General purpose sequence generator which includes 35-stage field shift register determines mathematical properties of polynomials such as divisibility, period, order of roots, and other parameters that effect desirability of various sequences for specific applications; for example, irreducible polynomials which characterize sequences with randomness properties

Theory and calculus of cubical complexes

Combination switching networks with multiple outputs may be represented by Boolean functions. Report has been prepared which describes derivation and use of extraction algorithm that may be adapted to simplification of such simultaneous Boolean functions

Generation of key in cryptographic system for secure communications

Report discusses key generation for transmission of confidential data. A number of feedback functions are discussed for generation of long key sequences

Binary sequence detector uses minimum number of decision elements

Detector of an n bit binary sequence code within a serial binary data system assigns states to memory elements of a code sequence detector by employing the same order of states for the sequence detector as that of the sequence generator when the linear recursion relationship employed by the sequence generator is given

Linear Three-Tap Feedback Shift Register-Patent

Linear three-tap feedback shift registe

Improved feedback shift register

Design of feedback shift register with three tap feedback decoding scheme is described. Application for obtaining sequence synchronization patterns is examined. Operation of the circuitry is described and drawings of the systems are included

A m-ary linear feedback shift register with binary logic

A family of m-ary linear feedback shift registers with binary logic is disclosed. Each m-ary linear feedback shift register with binary logic generates a binary representation of a nonbinary recurring sequence, producible with a m-ary linear feedback shift register without binary logic in which m is greater than 2. The state table of a m-ary linear feedback shift register without binary logic, utilizing sum modulo m feedback, is first tubulated for a given initial state. The entries in the state table are coded in binary and the binary entries are used to set the initial states of the stages of a plurality of binary shift registers. A single feedback logic unit is employed which provides a separate feedback binary digit to each binary register as a function of the states of corresponding stages of the binary registers