Entwurf und Analyse von Integrierten CMOS Hochspannungs-Treibern in Niederspannungs-Technologien

With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors. Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40% and 46%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail. In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.Mit der Skalierung der CMOS-Technologie wurde die Nominal-Spannung der I/O Transistoren von 5,0 V in 0,25-um Prozess auf 2,5 V in 65-nm reduziert. Es kann jedoch nicht die Versorgungsspannung von einigen Anwendungen mit derselben Rate verringert werden. Daher werden hochspannungskompatible Transistoren für die Schaltungsentwicklung eingesetzt, aber diese speziellen Komponenten sind noch nicht für die neuentwickelten Technologien verfügbar und werden erst in einiger Zeit einsatzbereit sein. Daher ist die Kaskadierung von einzelnen Standard MOS-Transistoren vorteilhaft, da nicht nur eine erhöhte Spannungsfestigkeit erreicht wird, sondern diese Methode Technologie- Unabhängigkeit bietet und volle Integration mit digitalen Schaltungen, System-On-Chip, ermöglicht. Jedoch haben die Hochspannungs- (HV-) Schaltungen basierend auf dieser Methode, wie Treiber, die Abwärtswandler umschalten, einen niedrigen Wirkungsgrad aufgrund des hohen On-Widerstandes durch die gestapelten Transistoren. Das Ziel dieser Arbeit ist, einen HV-Treiber mit einem minimalen On-Widerstand zu entwickeln. Um das zu erreichen, wird zuerst die Gate-Spannung jedes gestapelten Transistors zum Antreiben mit dem maximalen Strom im Pull-up und Pull-down-Pfad des HV-Treibers für verschiedene Versorgungsspannungen berechnet. Diese Berechnung wird mit Hilfe des Computer-Algebra-Systems MAXIMA durchgeführt. Im Hinblick auf die Ergebnisse, die in mathematischen Formeln erfolgen, wird eine Methodologie für Schaltungsentwürfe dargestellt, um die erforderten Gate-Spannungen zu generieren. Auf Basis dieser Design-Methodik, wird ein 2- und ein 3-fach gestapelter CMOS HV-Treiber in 65-nm-TSMC Technologie mit I/O-Standard-Transistoren mit einer Nennspannung von 2,5 V entworfen. Die Simulationsergebnisse zeigen, dass die generierten Gate-Spannungen in etwa den Idealwerten entsprechen. Für die maximal zulässigen Versorgungsspannungen von 5,0 V und 7,5 V, sind die Pull-up On-Widerstände der entwickelten HV-Treiber etwa 36% und die Pull-down On-Widerstände 40% und 46% im Vergleich zu einer früher veröffentlichten Arbeit verbessert. Für die Umschaltung eines Abwärtswandlers wird der entworfene 3-fach gestapelte CMOS HV-Treiber durch Erhöhung der Transistoren-Anzahl in jedem Stapel optimiert, und als 3HVDv1 definiert. Die Schaltung hat eine Fläche von etwa 0.187 mm² und ist auf Chips implementiert. Zwei verschiedene Gehäusetechnologien (Chip-in-Package und Chip-on-Board) wurden gefertigt. Neben diesem Hauptziel, verbesserte 3- und 4-fach gestapelte CMOS HV-Treiber, 3HVDv2 und 4HVDv3, zu entwerfen; ist jedoch der zweite Treiber eine verbesserte Form des ersten und kann für Versorgungsspannungen im Bereich von 3,5 V bis 7,5 V, der eine Erweiterung von 66% im Vergleich zu üblichen Treiber aufweist, angewendet werden. Aufgrund des Selbstvorspannungs-Verfahren, werden die Haupttransistoren des Treibers ohne zusätzliche Referenzspannung für die aktive Pull-Down und Pull-Up Zustände reguliert

Asymmetry of the Receding Hairline in Men With Early Androgenetic Alopecia

Background: The Norwood classification system is commonly used to ascertain the progress of androgenetic alopecia (AGA) with a robust and quick assessment, but it lacks precision in the frontal region, notably during the onset of male pattern hair loss. Objective: Due to the ongoing technical improvement in restorative hair transplantation practices, we aim to develop simple quantitative methods for measuring the progression of AGA. Methods: Here, we used a quantitative system to evaluate the progress of AGA of the frontal receding hairline in a case study with 41 patients. Results: We found subtle differences in the extent of frontotemporal regressions that were not captured by the Norwood classification system. The majority of patients exhibited significantly larger right-sided frontotemporal regressions. Conclusion: These results indicate that the quantification system used is a valuable tool in complementing the Norwood classification system to more precisely determine the recessing hairline characteristics in early stages of hair loss. Our findings also suggest that hairline regression in AGA-affected patients is asymmetrical, a hitherto unnoticed disorder-associated phenomenon with unknown biological causality. </jats:sec

Post-Resettlement Intimate Partner Domestic Violence in Afghan and Arab Refugees: A Scoping Review

Intimate Partner Domestic Violence (IPDV) has been reported to be high in minorities across the US. Among minorities, refugees and immigrants encounter particular barriers that may influence their responses to IPDV. This scoping review examined three decades of literature (1980–2022) on resettled married Afghan and Arab refugee women’s attitudes and behaviors toward IPDV in their host countries, aiming to explore gaps in the research, practice, and policy recommendations. Based on the Arksey and O’Malley model, our scoping review conducted extensive searches in SCOPUS, PubMed, PsychInfo, CINAHL, the Web of Science, the Directory of Open Access Journals, and the Embase databases. Searches identified articles that examined resettled Afghan and/or Arab refugees’ responses to IPDV in Western countries. The search identified 439 unique citations; 17 met the inclusion/exclusion criteria. The major findings included acculturative changes in refugee attitudes and behaviors and in stakeholders’ perspectives. Significant attitudinal changes (acknowledgment, silence, justification, or IPDV disapproval) contrasted with less behavioral changes (help-seeking behaviors, or action plans), or changes in barriers to actions, and with a resistance to change in stakeholders (cultural norms and beliefs, the community patriarchal normalization of violence, service providers’ unfamiliarity with client diversity and refugee cultures) in supporting women’s decision-making regarding IPDV. Not a single article made explicit policy recommendations