A Study on the Small Groups for the Vitalization of Young Adult: with a Focus on Dang-IL Church

This thesis is a study on the revitalization plan for youth ministry in the church. The purpose of this study is to study the effect of small group ministry on faith growth and youth revitalization as a way to promote youth ministry based on the understanding of youth. Today, while the growth of Korean churches is slowing and the number of members decreases, the youth group has also stopped growing, facing a crisis of spiritual growth and a crisis of existence itself. The decline of the young generation is not a problem only today, but at a time when the next generation is rapidly decreasing, the future is darker. Currently, there is a need for a realistic alternative to the revitalization of youth and faith growth. Therefore, this researcher intends to face the reality of the ministry along with the recognition of the importance of youth ministry, and to clarify through a small group that a core ministry is necessary for activation. It will be suggested that small group ministry within the church is the essential ministry for church growth suggested by the Bible and plays an important role in the growth of the faith of young people. In order to discuss that small group ministry is the core of the youth ministry philosophy in the present time, I would like to do a real case study of biblical community and small group core ministries and small group activities. Based on this study, I would like to suggest a plan to revitalize the youth group through small groups as an improvement plan for church growth

A 22-pJ/spike 73-Mspikes/s 130k-compartment neural array transceiver with conductance-based synaptic and membrane dynamics

Neuromorphic cognitive computing offers a bio-inspired means to approach the natural intelligence of biological neural systems in silicon integrated circuits. Typically, such circuits either reproduce biophysical neuronal dynamics in great detail as tools for computational neuroscience, or abstract away the biology by simplifying the functional forms of neural computation in large-scale systems for machine intelligence with high integration density and energy efficiency. Here we report a hybrid which offers biophysical realism in the emulation of multi-compartmental neuronal network dynamics at very large scale with high implementation efficiency, and yet with high flexibility in configuring the functional form and the network topology. The integrate-and-fire array transceiver (IFAT) chip emulates the continuous-time analog membrane dynamics of 65 k two-compartment neurons with conductance-based synapses. Fired action potentials are registered as address-event encoded output spikes, while the four types of synapses coupling to each neuron are activated by address-event decoded input spikes for fully reconfigurable synaptic connectivity, facilitating virtual wiring as implemented by routing address-event spikes externally through synaptic routing table. Peak conductance strength of synapse activation specified by the address-event input spans three decades of dynamic range, digitally controlled by pulse width and amplitude modulation (PWAM) of the drive voltage activating the log-domain linear synapse circuit. Two nested levels of micro-pipelining in the IFAT architecture improve both throughput and efficiency of synaptic input. This two-tier micro-pipelining results in a measured sustained peak throughput of 73 Mspikes/s and overall chip-level energy efficiency of 22 pJ/spike. Non-uniformity in digitally encoded synapse strength due to analog mismatch is mitigated through single-point digital offset calibration. Combined with the flexibly layered and recurrent synaptic connectivity provided by hierarchical address-event routing of registered spike events through external memory, the IFAT lends itself to efficient large-scale emulation of general biophysical spiking neural networks, as well as rate-based mapping of rectified linear unit (ReLU) neural activations

Conceptual Design of a Solid State Telescope for Small scale magNetospheric Ionospheric Plasma Experiments

The present paper describes the design of a Solid State Telescope (SST) on board the Korea Astronomy and Space Science Institute satellite-1 (KASISat-1) consisting of four [TBD] nanosatellites. The SST will measure these radiation belt electrons from a low-Earth polar orbit satellite to study mechanisms related to the spatial resolution of electron precipitation, such as electron microbursts, and those related to the measurement of energy dispersion with a high temporal resolution in the sub-auroral regions. We performed a simulation to determine the sensor design of the SST using GEometry ANd Tracking 4 (GEANT4) simulations and the Bethe formula. The simulation was performed in the range of 100 ~ 400 keV considering that the electron, which is to be detected in the space environment. The SST is based on a silicon barrier detector and consists of two telescopes mounted on a satellite to observe the electrons moving along the geomagnetic field (pitch angle 0°) and the quasi-trapped electrons (pitch angle 90°) during observations. We determined the telescope design of the SST in view of previous measurements and the geometrical factor in the cylindrical geometry of Sullivan (1971). With a high spectral resolution of 16 channels over the 100 keV ~ 400 keV energy range, together with the pitch angle information, the designed SST will answer questions regarding the occurrence of microbursts and the interaction with energetic particles. The KASISat-1 is expected to be launched in the latter half of 2020

Large Scale Asynchronous Low-power VLSI Systems for Event- driven Sensory and Neural Processing

This dissertation investigates a low-power temporal event encoding imaging sensory system front end and a neural computation analog VLSI backend embedded within a custom scalable architecture enabling highly energy efficient processing of these event streams. We explore the differences in event encoding and conventional computing emphasizing that computation and communication are data- driven and energy costs scale with information transfer and processing. The application of this principle in the imaging sensory system increases efficiency by ensuring that light intensity information is gathered only when and where warranted by temporal change and spatial proximity. This temporal contrast detection imager having 128x128 pixel array die size of 5x5mm² and pixel size of 33x33[mu]m² is fabricated in 0.18[mu]m CMOS. With supporting asynchronous event-driven information compression we achieved 1.52nJ per pixel event detection and readout. Similarly for neural computation slow but densely arrayed neural units are fabricated on a 4x4mm² die in 90nm CMOS. We present a 65-k integrate-and-fire array transceiver (IFAT) on a single die implementing 65-k neurons each with two compartments and four conductance based programmable analog synapses at 18.2 Mevents/s per each quadrant at sustained peak synaptic event throughput and 22pJ per synaptic input event in average. Operating at very low power the IFAT is robust to noisy inputs and high throughput is enabled by an asynchronous two-tier micro- pipelining scheme. This system is formed in a tree based hierarchical address event routing (HiAER) architecture. HiAER is implemented in 5 Xilinx Spartan-6 FPGAs enabling 262k neurons and 262M synapses on a level of hierarchy, at 3.6x10⁷ synaptic events per second per each 16k-neuron node in the hierarch

A 22-pJ/spike 73-Mspikes/s 130k-compartment neural array transceiver with conductance-based synaptic and membrane dynamics

Neuromorphic cognitive computing offers a bio-inspired means to approach the natural intelligence of biological neural systems in silicon integrated circuits. Typically, such circuits either reproduce biophysical neuronal dynamics in great detail as tools for computational neuroscience, or abstract away the biology by simplifying the functional forms of neural computation in large-scale systems for machine intelligence with high integration density and energy efficiency. Here we report a hybrid which offers biophysical realism in the emulation of multi-compartmental neuronal network dynamics at very large scale with high implementation efficiency, and yet with high flexibility in configuring the functional form and the network topology. The integrate-and-fire array transceiver (IFAT) chip emulates the continuous-time analog membrane dynamics of 65 k two-compartment neurons with conductance-based synapses. Fired action potentials are registered as address-event encoded output spikes, while the four types of synapses coupling to each neuron are activated by address-event decoded input spikes for fully reconfigurable synaptic connectivity, facilitating virtual wiring as implemented by routing address-event spikes externally through synaptic routing table. Peak conductance strength of synapse activation specified by the address-event input spans three decades of dynamic range, digitally controlled by pulse width and amplitude modulation (PWAM) of the drive voltage activating the log-domain linear synapse circuit. Two nested levels of micro-pipelining in the IFAT architecture improve both throughput and efficiency of synaptic input. This two-tier micro-pipelining results in a measured sustained peak throughput of 73 Mspikes/s and overall chip-level energy efficiency of 22 pJ/spike. Non-uniformity in digitally encoded synapse strength due to analog mismatch is mitigated through single-point digital offset calibration. Combined with the flexibly layered and recurrent synaptic connectivity provided by hierarchical address-event routing of registered spike events through external memory, the IFAT lends itself to efficient large-scale emulation of general biophysical spiking neural networks, as well as rate-based mapping of rectified linear unit (ReLU) neural activations