On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of tFE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., ION, SS, ION/IOFF and Cgg) by varying tFE up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum tFE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum tFE. Further, we analyze the impact of tFE on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with tFE. However, the WNM in general follows a non monotonic trend w.r.t tFE, and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized

Unveiling the Impact of IR-Drop on Performance Gain in NCFET-Based Processors

Negative capacitance field-effect transistor (NCFET) pushes the subthreshold swing beyond its fundamental limit of 60 mV/decade by incorporating a ferroelectric material within the gate-stack of transistor. Such a material manifests itself as an NC that provides an internal voltage amplification for the transistor resulting in higher ON-current levels. Hence, the performance of processors can be boosted while the operating voltage still remains the same. However, having an NC makes the total gate terminal capacitance larger. Although the impact of that on compensating the gained performance has already been studied in the literature, this paper is the first to explore the impact of NC on exacerbating the IR-drop problem in processors. In fact, voltage fluctuation in the power delivery network (PDN) due to IR-drops is one of the prominent sources of performance loss in processors, which necessitates adding timing guardbands to sustain a reliable operation during runtime. In this paper, we study NC-FinFET standard cells and processor for the 7-nm technology node. We demonstrate that NC, on the one hand, results in larger IR-drops due to the increase in current densities across the chip, which leads to a higher stress on the PDN. However, the internal voltage amplification provided by NC, on the other hand, compensates to some degree the voltage reduction caused by IR-drop. We investigate, from physics all the way to full-chip (GDSII) level, how the overall performance of a processor is affected under the impact that NC has on magnifying and compensating IR-drop

FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices

We present a massively parallel, 3D phase-field simulation framework for modeling ferroelectric materials based scalable logic devices. This code package, FerroX, self-consistently solves the time-dependent Ginzburg Landau (TDGL) equation for ferroelectric polarization, Poisson's equation for electric potential, and charge equation for carrier densities in semiconductor regions. The algorithm is implemented using the AMReX software framework [1], which provides effective scalability on manycore and GPU-based supercomputing architectures. We demonstrate the performance of the algorithm with excellent scaling results on NERSC multicore and GPU systems, with a significant (15×) speedup on the GPU using a node-by-node comparison. We further demonstrate the applicability of the code in simulations of ferroelectric domain-wall induced negative capacitance (NC) effect in Metal-Ferroelectric-Insulator-Metal (MFIM) and Metal-Ferroelectric-Insulator-Semiconductor-Metal (MFISM) devices. The charge (Q) v.s. voltage (V) responses for these 3D structures clearly indicate stabilized negative capacitance with multidomain formation, which is corroborated by amplification of the voltage at the interface between the ferroelectric and dielectric layers

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs

Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the cornerstone in bringing large-scale quantum processors to reality. The major challenges are, however, the tight power budget (in the order of milliwatts) and small latency (in the order of microseconds) requirements that such circuits inevitably must fulfill when operating at cryogenic temperatures. In-memory computing (IMC) is rapidly emerging as an attractive paradigm that holds the promise of performing computations efficiently where the data does not need to move back and forth between the CPU and the memory. Hence, it overcomes the fundamental bottleneck in classical von Neumann architectures, which provides considerable savings in power and latency. In this work, for the first time, we propose and implement an end-to-end approach that investigates SRAM-based IMC for cryogenic CMOS. To achieve that, we first characterize commercial 5 nm FinFETs from 300 K down to 10 K. Then, we employ the first cryogenic-aware industry-standard compact model for the FinFET technology (BSIM-CMG) to empower SPICE to accurately capture how cryogenic temperatures alter the electrical characteristics of transistors (e.g., threshold voltage, carrier mobility, sub-threshold slope, etc.). Our key contributions span from (1) carefully calibrating the cryogenic-aware BSIM-CMG against commercial 5 nm FinFET measurements in which SPICE simulations come with an excellent agreement with the experimental data, (2) exploring how the robustness of SRAM cells against noise (during the hold, read, and write operations) changes at extremely low temperatures, (3) investigating how the behavior of SRAM-based IMC circuits changes at 10 K compared to 300 K, and (4) modeling the error probabilities of IMC circuits that are used to calculate the Hamming distance, which is one of the essential similarity calculations to perform classifications

Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance - part II : model validation

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation.7 page(s

Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance - part I : model description

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau-Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.5 page(s