Reconfigurable network systems and software-defined networking

Modern high-speed networks have evolved from relatively static networks to highly adaptive networks facilitating dynamic reconfiguration. This evolution has influenced all levels of network design and management, introducing increased programmability and configuration flexibility. This influence has extended from the lowest level of physical hardware interfaces to the highest level of network management by software. A key representative of this evolution is the emergence of softwaredefined networking (SDN). In this paper, we review the current state of the art in reconfigurable network systems, covering hardware reconfiguration, SDN, and the interplay between them. We take a top-down approach, starting with a tutorial on software-defined networks. We then continue to discuss programming languages as the linking element between different levels of software and hardware in the network. We review electronic switching systems, highlighting programmability and reconfiguration aspects, and describe the trends in reconfigurable network elements. Finally, we describe the state of the art in the integration of photonic transceiver and switching elements with electronic technologies, and consider the implications for SDN and reconfigurable network systems.This work was jointly supported by the UKs Engineering and Physical Sciences Research Council (EPSRC) Internet Project EP/H040536/1, an EPSRC Research Fellowship grant to Philip Watts (EP/I004157/2), and DARPA and AFRL under contract FA8750-11-C-0249.This is the final version of the article. It first appeared from IEEE via http://dx.doi.org/10.1109/JPROC.2015.243573

Towards zero latency photonic switching in shared memory networks

Photonic networks-on-chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper we explore techniques which intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for a signi cant proportion of memory transactions. We then show how this technique can be applied to multiple-socket shared memory systems with low latency and energy consumption penalties. Finally, we present ideas and initial results to demonstrate that cache miss prediction could be used to set up photonic circuits for more complex memory transactions and main memory accesses

Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Optical Network on Chips (NoCs) based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, typically of the order of 8-256B. Messages of this length create high overhead for optical switching systems due to arbitration and switching times. Current schemes only start the arbitration process when the message arrives at the input buffer of the network. In this paper, we propose a scheme which intelligently uses the information from the memory controllers to schedule optical paths. We identified predictable patterns of messages associated with memory operations for a 32 core x86 system using the MESI coherency protocol. We used the first message of each pattern to open the optical paths which will be used by all subsequent messages thereby eliminating arbitration time for the latter. Without considering the initial request message, this scheme can therefore reduce the time of flight of a data message in the network by 29% and that of a control message by 67%. We demonstrate the benefits of this scheduling algorithm for applications in the PARSEC benchmark suite with overall average reductions in overhead latency per message, of 31.8% for the streamcluster benchmark and 70.6% for the swaptions benchmark

Experimental demonstration of an ultra-low latency control plane for optical packet switching in data center networks

Optical interconnection networks have the potential to reduce latency and power consumption while increasing the bisection bandwidth of data center networks compared to electrical network architectures. Optical circuit-switched networking has been proposed but it is reconfigurable in milliseconds. Although switches operating on nanosecond timescales have been demonstrated, centrally scheduling such switching architectures is considered to be of high complexity, incurring significant delay penalties on the total switching latency. In this paper we present a high-speed control plane design based on a central switch scheduler for nanosecond optical switching which significantly reduces the end-to-end latency in the network compared to using the best electronic switches. We discuss the implementation of our control plane on field-programmable gate array (FPGA) boards and quantify its delay components. We focus on the output-port allocation circuit design which limits the scheduling delay and the end-to-end latency. Using our FPGA-implemented control plane, for a 32 × 32 switch, we experimentally demonstrate rack-scale optical packet switching with a minimum end-to-end head-to-tail latency of 71.0 ns, outperforming current state-of-the-art electronic switches. The effect of asynchronous control plane operation on the switch performance is evaluated experimentally. Finally, a new parallel allocation circuit design is presented decreasing the scheduling delay by 42.7% and the minimum end-to-end latency to 54.6 ns. More importantly, it enables scaling to a switch double the size (64 × 64) with a minimum end-to-end latency less than 71.0 ns. In a developed cycle-accurate network emulator we demonstrate nanosecond switching up to 60% of port capacity and average end-to-end latency less than 10 μs at full capacity while maintaining zero packet loss across all traffic loads

Co-creation of information leaflets to meet the support needs of people living with Complex Regional Pain Syndrome (CRPS) through innovative use of wiki technology

Objective: People living with Complex Regional Pain Syndrome (CRPS) experience frustration with the lack of knowledge and understanding of CRPS as a pain condition. We report on our attempt to address this issue. Method: People living with CRPS taking part in a larger study were invited to co-construct a CRPS wiki page that addressed the areas in which they had experienced the most difficulty. A blank wiki page was set up for participants to populate with issues they felt needed to be raised and addressed. Results: Participants failed to engage with the wiki technology. We modified our procedure and completed an inductive analysis of a sister-forum which participants were using as part of the larger study. Six issues of importance were identified. We used the discussion forum threads to populate the themes. Due to a continued lack of engagement with the wiki technology, the team decided to create a suite of leaflets which were piloted with delegates at a CRPS patient conference. Conclusions: Future work should be mindful of the extent to which patients are able and willing to share their experiences through such technology. Striking the balance between patient-endorsed and researcher-driven co-creation of such material is imperative

Study protocol: A phase III randomised, double-blind, parallel arm, stratified, block randomised, placebo-controlled trial investigating the clinical effect and cost-effectiveness of sertraline for the palliative relief of breathlessness in people with chronic breathlessness

© Published by the BMJ Publishing Group Limited. Introduction: Breathlessness remains a highly prevalent and distressing symptom for many patients with progressive life-limiting illnesses. Evidence-based interventions for chronic breathlessness are limited, and there is an ongoing need for high-quality research into developing management strategies for optimal palliation of this complex symptom. Previous studies have suggested that selective serotonin reuptake inhibitors such as sertraline may have a role in reducing breathlessness. This paper presents the protocol for a large, adequately powered randomised study evaluating the use of sertraline for chronic breathlessness in people with progressive life-limiting illnesses. Methods and analysis: A total of 240 participants with modified Medical Research Council Dyspnoea Scale breathlessness of level 2 or higher will be randomised to receive either sertraline or placebo for 28 days in this multisite, double-blind study. The dose will be titrated up every 3 days to a maximum of 100 mg daily. The primary outcome will be to compare the efficacy of sertraline with placebo in relieving the intensity of worst breathlessness as assessed by a 0-100 mm Visual Analogue Scale. A number of other outcome measures and descriptors of breathlessness as well as caregiver assessments will also be recorded to ensure adequate analysis of participant breathlessness and to allow an economic analysis to be performed. Participants will also be given the option of continuing blinded treatment until either study data collection is complete or net benefit ceases. Appropriate statistical analysis of primary and secondary outcomes will be used to describe the wealth of data obtained. Ethics and dissemination: Ethics approval was obtained at all participating sites. Results of the study will be submitted for publication in peer-reviewed journals and the key findings presented at national and international conferences. Trial registration number ACTRN12610000464066

Why Are Male Social Relationships Complex in the Doubtful Sound Bottlenose Dolphin Population?

Copyright 2008 Elsevier B.V., All rights reserved.Peer reviewedPublisher PD

Power Optimized Transceivers for Future Switched Networks

Network equipment power consumption is under increased scrutiny. To understand and decompose transceiver power consumption, we have created a toolkit incorporating a library of transceiver circuits in 45-nm CMOS and MOS current mode logic (MCML) and characterize power consumption using representative network traffic traces with digital synthesis and SPICE tools. Our toolkit includes all the components required to construct a library of different transceivers: line coding, frame alignment, channel bonding, serialization and deserialization, clock–data recovery, and clock generation. For optical transceivers, we show that photonic components and front end drivers only consume a small fraction (<22%) of total serial transceiver power. This implies that major reductions in optical transceiver power can only be obtained by paying attention to the physical layer circuits such as clock recovery and serial–parallel conversions. We propose a burst-mode physical layer protocol suitable for optically switched links that retains the beneficial transmission characteristics of 8b/10b, but, even without power gating and voltage controlled oscillator power optimization, reduces the power consumption during idle periods by 29% compared with a conventional 8b/10b transceiver. We have made the toolkit available to the community at large in the hope of stimulating work in this field