Implementation techniques of high-order FFT into low-cost FPGA

International audienceIn this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/are

Sensitivity of optical correlation to color change of target images

International audienceOptical correlation is based on the comparison of contours between an unknown target image and a known reference image. However, it does not usually include the color image information in the decision making process. In order to render the correlation method sensitive to color change, we propose a general method based on the decomposition of the target image in its three color components using, either the normalized RGB (red, green, blue) color space, or the normalized HSV (hue, saturation, value) space. Then, the correlation operation is carried out for each color component and the results are merged in order to make a decision. The aforementioned steps can alleviate some of the problems associated with illumination changes in the target image but do utilize color information of the target image. To overcome these problems, we propose to convert the color information in contour information into a signature corresponding to the color information of the target image. This technique and test results are presented to validate its effectiveness. The preliminary results obtained with this technique are encouraging

Contribution à la définition, à l'optimisation et à l'implantation d'IP de traitement du signal et des données en temps réel sur des cibles programmables

The main objective of this thesis is to realize a numerical implementation of optical methods of image and signal processing. To achieve this end, we opted to use FPGA (Field Programmable Gate Array) and GPU (Graphical Processing Unit) devices. This choice is justified by their high performance in terms of speed. In addition, to improve productivity, we focused on the reuse of predesigned blocks or "Intellectual Properties" IP. While existing commercial IP are optimized, they are often paid and highly dependent on the card. The first contribution is to provide an optimized IP for Fourier transform (FFT) and the cosine transform (DCT) computing. Indeed, the choice of these two transformations is justified by the widespread use of these two transforms (FFT and DCT), particularly in pattern recognition and compression algorithms. The second contribution is to validate the operation of the proposed IP using a bench test. The last contribution is to implement on FPGA and GPU applications for pattern recognition and compression. One of the convincing results obtained in this thesis is to propose an IP for FFT computing three times faster than Xilinx IP and thus to achieve 4700 correlations per second.En dépit du succès que les implantations optiques des applications de traitement d'images ont connu, le traitement optique de l'information suscite aujourd'hui moins d'intérêt que dans les années 80-90. Ceci est dû à l'encombrement des réalisations optiques, la qualité des images traitées et le coût des composants optiques. De plus, les réalisations optiques ont eu du mal à s’affranchir de l’avènement des circuits numériques. C’est dans ce cadre que s’inscrivent les travaux de cette thèse dont l’objectif est de proposer une implantation numérique des méthodes optiques de traitement d’images. Pour réaliser cette implantation nous avons choisi d’utiliser les FPGA et les GPU grâce aux bonnes performances de ces circuits en termes de rapidité. En outre, pour améliorer la productivité nous nous sommes focalisés à la réutilisation des blocs préconçus ou IP « Intellectual Properties ». Malgré que les IP commerciales existantes soient optimisées, ces dernières sont souvent payantes et dépendent de la famille de la carte utilisée. La première contribution est de proposer une implantation optimisée des IP pour le calcul de la transformée de Fourier FFT et de la DCT. En effet, le choix de ces deux transformations est justifié par l'utilisation massive de ces deux transformées (FFT et DCT), dans les algorithmes de reconnaissance de formes et de compression, respectivement. La deuxième contribution est de valider le fonctionnement des IP proposées par un banc de test et de mesure. Enfin, la troisième contribution est de concevoir sur FPGA et GPU des implantations numériques des applications de reconnaissance de formes et de compression. Un des résultats probant obtenu dans cette thèse consiste à avoir une rapidité de l’IP FFT proposée 3 fois meilleure que celle de l’IP FFT Xilinx et de pouvoir réaliser 4700 corrélations par seconde

Contribution to the definition, optimization and implementation of signal processing IPs on programmable target

En dépit du succès que les implantations optiques des applications de traitement d'images ont connu, le traitement optique de l'information suscite aujourd'hui moins d'intérêt que dans les années 80-90. Ceci est dû à l'encombrement des réalisations optiques, la qualité des images traitées et le coût des composants optiques. De plus, les réalisations optiques ont eu du mal à s’affranchir de l’avènement des circuits numériques. C’est dans ce cadre que s’inscrivent les travaux de cette thèse dont l’objectif est de proposer une implantation numérique des méthodes optiques de traitement d’images. Pour réaliser cette implantation nous avons choisi d’utiliser les FPGA et les GPU grâce aux bonnes performances de ces circuits en termes de rapidité. En outre, pour améliorer la productivité nous nous sommes focalisés à la réutilisation des blocs préconçus ou IP « Intellectual Properties ». Malgré que les IP commerciales existantes soient optimisées, ces dernières sont souvent payantes et dépendent de la famille de la carte utilisée. La première contribution est de proposer une implantation optimisée des IP pour le calcul de la transformée de Fourier FFT et de la DCT. En effet, le choix de ces deux transformations est justifié par l'utilisation massive de ces deux transformées (FFT et DCT), dans les algorithmes de reconnaissance de formes et de compression, respectivement. La deuxième contribution est de valider le fonctionnement des IP proposées par un banc de test et de mesure. Enfin, la troisième contribution est de concevoir sur FPGA et GPU des implantations numériques des applications de reconnaissance de formes et de compression. Un des résultats probant obtenu dans cette thèse consiste à avoir une rapidité de l’IP FFT proposée 3 fois meilleure que celle de l’IP FFT Xilinx et de pouvoir réaliser 4700 corrélations par seconde.The main objective of this thesis is to realize a numerical implementation of optical methods of image and signal processing. To achieve this end, we opted to use FPGA (Field Programmable Gate Array) and GPU (Graphical Processing Unit) devices. This choice is justified by their high performance in terms of speed. In addition, to improve productivity, we focused on the reuse of predesigned blocks or "Intellectual Properties" IP. While existing commercial IP are optimized, they are often paid and highly dependent on the card. The first contribution is to provide an optimized IP for Fourier transform (FFT) and the cosine transform (DCT) computing. Indeed, the choice of these two transformations is justified by the widespread use of these two transforms (FFT and DCT), particularly in pattern recognition and compression algorithms. The second contribution is to validate the operation of the proposed IP using a bench test. The last contribution is to implement on FPGA and GPU applications for pattern recognition and compression. One of the convincing results obtained in this thesis is to propose an IP for FFT computing three times faster than Xilinx IP and thus to achieve 4700 correlations per second

AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE

International audienc

Low complexity DCT engine for image and video compression

International audienceIn this paper, we defined a low complexity 2D-DCT architecture. The latter will be able to transform spatial pixels to spectral pixels while taking into account the constraints of the considered compression standard. Indeed, this work is our first attempt to obtain one reconfigurable multistandard DCT. Due to our new matrix decomposition, we could define one common 2D-DCT architecture. The constant multipliers can be configured to handle the case of RealDCT and/or IntDCT (multiplication by 2). Our optimized algorithm not only provides a reduction of computational complexity, but also leads to scalable pipelined design in systolic arrays. Indeed, the 8 × 8 StdDCT can be computed by using 4×4 StdDCT which can be obtained by calculating 2×2 StdDCT. Besides, the proposed structure can be extended to deal with higher number of N (i.e. 16 × 16 and 32 × 32). The performance of the proposed architecture are better when compared with conventional designs. In particular, for N = 4, it is found that the proposed design have nearly third the area-time complexity of the existing DCT structures. This gain is expected to be higher for a greater size of 2D-DCT

Implementation techniques of high-order FFT into low-cost FPGA

International audienceIn this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/are

Fast Face Recognition Approach Using a Graphical Processing Unit "GPU"

International audienceIn this manuscript, we present an implementation of a correlation method for face recognition application on GPU. Our correlator is based on the famous "4f" setup and the use of a Phase Only Filter (POF). Traditionally, the correlation method is implemented using optical components for real-time application. Unfortunately, optical implementation is complex and has exorbitant price. To cope with these drawbacks and in order to benefit from the accuracy of the correlation method, we propose in this work to implement the correlation using GPU. To this end, we will take an interest in the mathematical aspect of the correlation method to identify the processing to be implemented on GPU. Simulations results about the implementation of the face recognition application on GPU showed the efficiency of our proposed design. Moreover, comparison between GPU and CPU in terms of execution time have been made and shows that, to identify one face among 4, GPU Nvidia Geforce 8400 GS is 3 times faster than the Intel Core 2 CPU 2.00 GHZ (using Matlab)

Implementation techniques of high-order FFT into low-cost FPGA

International audienceIn this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/area