CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers

Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handling of incoming events. However, RISC- V processors are still lagging in this area compared to more mature proprietary architectures, such as ARM Cortex-M and TriCore, which have been tuned for years. The default interrupt controller standardized by RISC-V, the Core Local Interruptor (CLINT), lacks configurability in prioritization and preemption of interrupts. The RISC-V Core Local Interrupt Controller (CLIC) specification addresses this concern by enabling pre-emptible, low-latency vectored interrupts while also envisioning optional extensions to improve interrupt latency. In this work, we implement a CLIC for the CV32E40P, an industrially supported open-source 32-bit MCU-class RISC-V core, and enhance it with fastirq: a custom extension that provides interrupt latency as low as 6 cycles. We call CV32RT our enhanced core. To the best of our knowledge, CV32RT is the first fully open-source RV32 core with competitive interrupt-handling features compared to the Arm Cortex-M series and TriCore. The proposed extensions are also demonstrated to improve task context switching in real-time operating systems.Comment: 12 pages, submitted to IEEE Transactions on VLSI Systems (TVLSI

Two-tier blockchain timestamped notarization with incremental security

Digital notarization is one of the most promising services offered by modern blockchain-based solutions. We present a digital notary design with incremental security and cost reduced with respect to current solutions. A client of the service receives evidence in three steps. In the first step, evidence is received almost immediately, but a lot of trust is required. In the second step, less trust is required, but evidence is received seconds later. Finally, in the third step evidence is received within minutes via a public blockchain.Comment: Accepted for presentation at the 2nd Distributed Ledger Technology Workshop (DLT 2019), Pis

Synthesis of Amphiphilic Hydantoin-based Universal Peptidomimetics as Antibiotic Agents

Three model hydantoin-based universal peptidomimetics are designed and synthetized. Their preferred amphiphilic -turn conformation was assessed by molecular modeling and NMR experiments, and their antibacterial acivity tasted against Gram positive and Gram negative bacteria strains, demostrating that these compounds could be a captivating class of antibiotic to fight emergent drug resistanc

Peak nasal inspiratory flow and peak expiratory flow. Upright and sitting values in an adult population

Background: Nasal obstruction is correlated with a decreased quality of life . An easy way to evaluate nasal patency is the peak nasal inspiratory flow (PNIF) measurement. Normal PNIF values have been published by many authors. However, some authors evaluated volunteers in a sitting position, while others have measured PNIF values in standing volunteers. Body position has been shown to influence pulmonary function, with differences between sitting and upright positions. As nasal and pulmonary flows are strictly related, the present pilot study tried to establish whether PNIF/PEF changed with body position in adults. Methodology/Principal: PNIF and PEF were measured in sitting and standing positions with the order of testing randomized in 76 healthy volunteers, 30 male (40 ±16 years). Results: In the group as a whole between sitting and upright position, PEF was significantly different (p=0.009), while PNIF showed a trend towards a significant difference (p=0.10). Conclusions: The present study, although showing a generally positive effect of the standing position on PEF values, does not show a clear effect on PNIF

A High-performance, Energy-efficient Modular DMA Engine Architecture

Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs) are critically needed to transfer data independently of the processing elements, hiding latency and achieving high throughput even for complex access patterns to high-latency memory. With the prevalence of heterogeneous systems, DMAEs must operate efficiently in increasingly diverse environments. This work proposes a modular and highly configurable open-source DMAE architecture called intelligent DMA (iDMA), split into three parts that can be composed and customized independently. The front-end implements the control plane binding to the surrounding system. The mid-end accelerates complex data transfer patterns such as multi-dimensional transfers, scattering, or gathering. The back-end interfaces with the on-chip communication fabric (data plane). We assess the efficiency of iDMA in various instantiations: In high-performance systems, we achieve speedups of up to 15.8x with only 1 % additional area compared to a base system without a DMAE. We achieve an area reduction of 10 % while improving ML inference performance by 23 % in ultra-low-energy edge AI systems over an existing DMAE solution. We provide area, timing, latency, and performance characterization to guide its instantiation in various systems.Comment: 14 pages, 14 figures, accepted by an IEEE journal for publicatio

Peak nasal inspiratory flow measurement and visual analogue scale in a large adult population

Nasal obstruction is the most common symptom in nasal diseases. It can be evaluated objectively, i.e. by means of peak nasal inspiratory flow (PNIF) measures and/or subjectively by means of validated questionnaires. However, it has been reported that there is a lack of reliable correlation between subjective and objective measurements of nasal obstruction. The aim of the present study was to evaluate the correlation between PNIF measurements and the subjective sensation of nasal obstruction measured by means of a visual analogue scale (VAS) in a large population of consecutive rhinologic patients

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant's thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads.Comment: 33 pages, 11 figure

Towards a RISC-V Open Platform for Next-generation Automotive ECUs

The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses considerable challenges to the automotive supply chain since the continuous addition of new hardware and network cabling is not considered tenable. The availability of modern heterogeneous multi-processor chips represents a unique opportunity to reduce vehicle costs by integrating multiple functionalities into fewer Electronic Control Units (ECUs). In addition, the recent improvements in open-hardware technology allow to further reduce costs by avoiding lock-in solutions. This paper presents a mixed-criticality multi-OS architecture for automotive ECUs based on open hardware and open-source technologies. Safety-critical functionalities are executed by an AUTOSAR OS running on a RISC-V processor, while the Linux OS executes more advanced functionalities on a multi-core ARM CPU. Besides presenting the implemented stack and the communication infrastructure, this paper provides a quantitative gap analysis between an HW/SW optimized version of the RISC-V processor and a COTS Arm Cortex-R in terms of real-time features, confirming that RISC-V is a valuable candidate for running AUTOSAR Classic stacks of next-generation automotive MCUs.Comment: 8 pages, 2023 12th Mediterranean Conference on Embedded Computing (MECO

The role of disposition to critical thinking in digital game-based learning

The relationship between the development of 21st-century skills and game-based learning is a field to explore. Among the 21-st century skills, critical thinking is one of the most analyzed skills. This study aims to deepen the relationship between learning and disposition to critical thinking (DCT) in the context of Serious Games (SGs). In particular, starting from the evidence of previous work, that highlighted a positive effect of the DCT on game performance, this study analyzes how the DCT also affects the explicit learning gained by the players. This work highlights that the DCT has a crucial role in explicit knowledge acquisition and how the improvement of game performance is a direct consequence of DCT through a path analysis methodology