An investigation of temperature sensitive electrical parameters for SiC power MOSFETs

This paper examines dynamic Temperature Sensitive Electrical Parameters (TSEPs) for SiC MOSFETs. It is shown that the output current switching rate (dIDS/dt) coupled with the gate current plateau (IGP) during turn-ON would be the most effective under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dIDS/dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance (RGEXT). However, as dIDS/dt is increased by using a small RGEXT, parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dIDS/dt is at the highest with maximum RGEXT, there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as well as the compromise between the increased switching loss and the potential to implement effective condition monitoring using the evaluated TSEPs

The effect of electrothermal nonuniformities on parallel connected SiC power devices under unclamped and clamped inductive switching

Nonuniformities in the electrothermal characteristics of parallel connected devices reduce overall reliability since power is not equally dissipated between the devices. Furthermore, a nonuniform rate of operational degradation induces electrothermal variations thereby accelerating the development of failure. This paper uses simulations and experiments to quantitatively and qualitatively investigate the impact of electrothermal variations on the reliability of parallel connected power devices under unclamped inductive switching (UIS) conditions. This is especially pertinent to SiC where small die areas mean devices are often connected in parallel for higher current capability. Measurements and simulations show that increasing the variation in the initial junction temperatures and switching rates between parallel connected devices under UIS reduces the total sustainable avalanche current by 10%. It is seen that the device with the lower junction temperature and lower switching rate fails. The measurements also show that the maximum sustainable avalanche energy for a given variation in junction temperature and switching rate increases with the avalanche duration, meaning that the effect of electrothermal variation is more critical with high power (high current and low inductor) UIS pulses compared with high energy (low current and high inductance) pulses. These results are important for condition monitoring and reliability analysis

Temperature sensitive electrical parameters for condition monitoring in SiC power MOSFETs

This paper presents an analysis of the turn ON transient for SiC power MOSFETs and defines a Temperature Sensitive Electrical Parameter (TSEP) which is suitable for condition monitoring. The drain current switching rate dIDS/dt and its temperature dependency have been measured and analysed for commercially available 1.2 kV/10 A, 1.2 kV/24 A and 1.2 kV/42 A SiC MOSFETs from Wolfspeed showing that at lower switching speeds, i.e. using high gate resistances, it can be a suitable TSEP for condition monitoring. The impact of temperature on the switching speed indicates that the current switching rate is a more effective TSEP for higher current rated devices and the evaluation of the switching losses suggests that the sacrifice in switching speed for enabling the ability of estimating the junction temperature is not a major trade-off

Temperature and switching rate dependence of crosstalk in Si-IGBT and SiC power modules

The temperature and dV/dt dependence of crosstalk has been analyzed for Si-IGBT and SiC-MOSFET power modules. Due to a smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot-through currents compared with similarly rated Si-IGBT modules in spite of switching with a higher dV/dt and with a lower threshold voltage. However, due to high voltage overshoots and ringing from the SiC Schottky diode, SiC modules exhibit higher shoot-through energy density and induce voltage oscillations in the dc link. Measurements show that the shoot-through current exhibits a positive temperature coefficient for both technologies, the magnitude of which is higher for the Si-IGBT, i.e., the shoot-through current and energy show better temperature stability in the SiC power module. The effectiveness of common techniques of mitigating shoot-through, including bipolar gate drives, multiple gate resistance switching paths, and external gate-source and snubber capacitors, has been evaluated for both technologies at different temperatures and switching rates. The results show that solutions are less effective for SiC-MOSFETs because of lower threshold voltages and smaller margins for negative gate bias on the SiC-MOSFET gate. Models for evaluating the parasitic voltage have also been developed for diagnostic and predictive purposes. These results are important for converter designers seeking to use SiC technology

Compact electrothermal reliability modeling and experimental characterization of bipolar latchup in SiC and CoolMOS power MOSFETs

In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs

An integrated approach of AHP-DEMATEL methods applied for the selection of allied hospitals in outpatient service

Nowadays, the citizens are more aware of high-quality medical care than ever. They pay much attention to medical treatment safety, instructions from physicians, and the overall service quality performed by the hospital. To manage a hospital successfully, the important goals are to attract and then retain as many patients as possible by meeting potential demands of various kinds of the patients. In this context the decision making process is important in order to achieve a strategic decision and strategy. When the decision making problem occurs there is usually a limited number of possible alternatives but a large number of criteria according to which the optimal solution is selected. It is important to use an appropriate approach. This study presents a hybrid methodological approach based on the Decision Making Trial and Evaluation Laboratory (DEMATEL) method and Analytic Hierarchy process method to define the best allied hospital for an integrated network of outpatient service. The goal of this paper is to present a methodological approach and a practical application of hybrid method in a real case study

BACTERIA ASSOCIATED WITH THE WEST INDIAN FRUIT FLY ANASTREPHA OBLIQUA (MACQUART) (DIPTERA: TEPHRITIDAE)

BACTERIA ASSOCIATED WITH THE WEST INDIAN FRUIT FLY ANASTREPHA OBLIQUA (MACQUART) (DIPTERA: TEPHRITIDAE

Enabling high reliability power modules : a multidisciplinary task

Reliability of power electronic systems is a major concern for application engineers in the automotive and power system sectors. Power electronic modules are one of the main sources of failure in wind energy conversion systems. Power electronic converters used in wind turbine electric drive trains, railway traction, more-electric-aircrafts, marine propulsion and grid connected systems like FACTS/HVDC require reliable power devices and modules. Wide bandgap semiconductors like SiC have demonstrated enlarged electrothermal Safe-Operating-Areas compared with silicon devices. However, the reliability of SiC power modules and packages has been identified as an area of potential weakness. Traditional packaging systems have been developed for Si hence the different thermomechanical properties of SiC cause different stresses in the packaging thereby potentially causing reduced reliability. This paper identifies some of the key areas for the development of reliable power electronic systems using SiC. The focus is on condition monitoring, packaging system innovation and thermomechanical stress analysis as a function of the mechanical properties of Si and SiC. Power cycling experiments and finite element models have been used to support the analysis

Failure and reliability analysis of a SiC power module based on stress comparison to a Si device

The superior electro-thermal properties of SiC power devices permit higher temperature of operation and enable higher power density compared with silicon devices. Nevertheless, the reliability of SiC power modules has been identified as a major area of uncertainty in applications which require high reliability. Traditional power module packaging methods developed for silicon chips have been adopted for SiC and the different thermomechanical properties cause different fatigue stresses on the solder layer of the chip. In this paper a 2-D Finite Element (FE) model has been developed to evaluate the stress performance and lifetime of the solder layer for Si devices, which has been validated using accelerated power cycling tests on Si IGBTs. The proposed model was extrapolated for SiC devices of the same voltage and current rating using the same solder material and the results show that under the same cyclic power loss profile the induced stress and strain energy in the die attach layer is much higher and concentrates on the die/solder interfacial area for SiC chips. Using the validated stress-based model, the lifetime can be quantified when SiC chips are used. This ability to extrapolate the available power cycling and lifetime data of silicon chips to silicon carbide chips would be a key element for developing reliable packaging methods for SiC devices