Double-Sampling Single-Loop EA Modulator Topologies for Broad-band Applications

This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement

Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios

This paper presents novel double-sampling cascaded sigma-delta modulator topologies for wideband applications. The proposed modulator structures employ finite impulse response (FIR) noise transfer function (NTF) to achieve the aggressive noise shaping with an additional zero at the half of the sampling frequency to alleviate the quantization noise folding. Cascading of the proposed modulator structures is very simple without any additional circuit requirements.Comisión Interministerial de Ciencia y Tecnología TIC2003-0235

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switchedcapacitor applications

ABSTRACT This paper presents a new fully differential operational transconductance amplifier (OTA) for low-voltage and fastsettling switched-capacitor circuits in digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling

A Fully Fail-Safe Capacitive-Based Charge Metering Method for Active Charge Balancing in Deep Brain Stimulation

Related to safety issues, charge balancing is a major concern in neural and functional electrical stimulation. This paper presents a capacitive-based charge metering method as a low-power and precise charge balancing method used in Deep Brain Stimulation (DBS). In contrast to the previously presented capacitive-based charge metering methods, the proposed method does not need any precise and high-speed comparator for net-zero charge detection. It is proven that this method is insensitive to the delay and the offset of its components. Consequently, using ultra-low power components in the charge balancer is feasible. Furthermore, the proposed method properly supports any stimulation mode and waveform. The proposed approach along with voltage and current mode pulse generators was validated in a 0.9% saline solution by using a DBS lead

A LOW-POWER FULLY INTEGRATED GAUSSIAN-MSK MODULATOR BASED ON THE SIGMA-DELTA FRACTIONAL-N FREQUENCY SYNTHESIS

ABSTRACT A fully integrated GMSK modulator in DRRS band is presented. All components of the transmitter except the power amplifier, including the loop filter and the oscillator are on-chip. Transistor and system level simulations demonstrate that the modulator meets the performance requirements of the DRRS standard. The circuit power consumption of the modulator at 1.4GHz is 37mW with a single 3V power supply, in a 0.6µm digital CMOS technology. Low power consumption of the modulator is due to the low-power frequency divider and low-power low-phase noise ring oscillator

A Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications

Neural recording systems are essential for understanding the brain and developing treatments for neurological disorders. Analog-to-digital converter (ADC) is among the required building blocks of neural recording systems, as they convert the brain's electrical signals into digital data that can be processed and analyzed by processing units. In this paper, a new nonlinear ADC for spike sorting in biomedical applications has been introduced. The ADC is implemented with MOSFET varactors and voltage-controlled oscillators (VCO). By exploiting the nonlinear capacitance characteristics of MOSFET varactors, the ADC has a parabolic quantization function to suppress background noise in biomedical signals. Furthermore, nonlinear digitization gives an effective resolution that is almost 0.11 bit more than its physical number of bits. The resolution of neural signals can vary from 3.1 bits in the low amplitude range to 9.11 bits in the high amplitude range. The circuit was designed and simulated using a 180 nm CMOS process, taking up 0.102 mm(2) of silicon area. While operating at the sampling frequency of 25 kS/s and a supply voltage of 1 Volt, this ADC dissipates 62.4 mu W