Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors

Thanks to aggressive scaling of transistor dimensions, computers have revolutionized our life. However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. This thesis addresses this challenge by proposing new methods to model, analyze and mitigate aging at microarchitecture-level and above

Potenziale für industrieübergreifendes Flottenlernen – KI-Mobilitätsdatenplattform zur Risikominimierung des automatisierten Fahrens

Ob in Transport, Logistik, im Individualverkehr oder im öffentlichen Nahverkehr – Verkehrsträger erreichen dank Künstlicher Intelligenz immer höhere Automatisierungsgrade. Automatisiertes Fahren kann helfen, die Verkehrssicherheit zu erhöhen, Verkehrsflüsse zu optimieren und Schadstoffemissionen zu reduzieren. Durch immer leistungsfähigere Verfahren der KI und des Maschinellen Lernens wird die Technologie des automatisierten Fahrens zunehmend verbessert, sodass sie in mehr als 99 Prozent der Situationen in Real-Tests funktioniert. Ein Restrisiko für mögliches Fehlverhalten tritt im Zusammenhang mit sogenannten Edge und Corner Cases (Grenz- und Übergangsfälle) auf. Für diese selten auftretenden Sonderfälle sind KI-Systeme unter Umständen nicht ausreichend trainiert und getestet. Um die Potenziale des industrieübergreifenden Flottenlernens zu erschließen, schlagen die Expertinnen und Experten der Arbeitsgruppe Mobilität und intelligente Verkehrssysteme der Plattform Lernende Systeme daher die Gründung einer gemeinschaftlichen KI-Mobilitätsdatenplattform vor. Diese Plattform soll den Austausch von Mobilitätsdaten ermöglichen und zur Risikominimierung beim automatisierten Fahren beitragen

Cross-Layer Approaches for an Aging-Aware Design Space Exploration for Microprocessors

Abstract-With the continuous scaling of CMOS technologies, maintaining the microprocessor reliability becomes a major design challenge. In particular, accelerated transistor aging is a serious reliability concern, as it considerably reduces the operational system lifetime. To address this issue, in this work cross-layer solutions for aging modeling, simulation and mitigation are proposed, to be able to co-optimize reliability together with the traditional design constraints such as power, performance, and cost. Therefore, the knowledge from several abstraction layers, ranging circuit-to architecture-level, are exploited for cost-effective aging-aware architecture and system design. The comprehensive simulations and experimental analysis performed in this work show the benefits of this approach over state-of-the-art single-layer solutions

Avoiding unnecessary write operations in STT-MRAM for low power implementation

Abstract—Spin Transfer Torque (STT) is a promising emerging memory technology because of its various advantages such as non-volatility, high density, virtually infinite endurance, scalability and CMOS compatibility. Despite all these features, high write current is still a challenge for its widespread use. When writing a value that is already stored, a significant current flows through the Magnetic Tunnel Junction (MTJ) cell which is almost the same as that required to flip the stored data. This increases the total power consumption of the memory. To address this issue, we propose a technique which can avoid unnecessary write operations with bit-level granularity. Our technique can save 68.9 % of the total write power consumption with a minor area overhead (0.68 %) and only a small timing penalty (1.33 %). Keywords—STT-MRAM, non-volatile memory, low power, write avoidance I

Architectural aspects in design and analysis of SOT-based memories

Abstract—Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its var-ious advantages such as non-volatility, high density and scala-bility. In particular, Spin Orbit Torque (SOT) MRAM is gain-ing interest as it comes along with all the benefits of its pre-decessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this work, we provide a very detailed analysis of SOT-MRAM at both circuit- and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that with a hybrid-combination of SRAM for the L1-cache and SOT-MRAM for the L2-cache the energy consumption can be reduced by 63 % in average while the performance can be increased by 1 %. In addition, the memory area is 43 % lower compared to an SRAM-only configuration. I

Architecting SOT-RAM Based GPU Register File

With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance