A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (/spl times/2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (/spl times/2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35/spl mu/m CMOS technology

Modeling of switched-capacitor delta-sigma Modulators in SIMULINK

Precise behavioral modeling of switched-capacitor /spl Delta//spl Sigma/ modulators is presented. Considering noise (switches' and op-amps' thermal noise), clock jitter, nonidealities of integrators and op-amps including finite dc-gain (DCG) and unity gain bandwidth, slew-limiting, DCG nonlinearities and the input parasitic capacitance, quantizer hysteresis, switches' clock-feedthrough, and charge injection, exhaustive behavioral simulations that are close models of the transistor-level ones can be performed. The DCG nonlinearity of the integrators, which is not considered in many /spl Delta//spl Sigma/ modulators' modeling attempts, is analyzed, estimated, and modeled. It is shown that neglecting this parameter would lead to a significant underestimation of the modulators' behavior and increase the noise floor as well as the harmonic distortion at the output of the modulator. Evaluation and validation of the models were done via behavioral and transistor-level simulations for a second-order modulator using SIMULINK and HSPICE with a generic 0.35-/spl mu/m CMOS technology. The effects of the nonidealities and nonlinearities are clearly seen when compared to the ideal modulator in the behavioral and actual modulator in the circuit-level environment

A pseudoclass-AB telescopic-cascode operational amplifier

ABSTRACT A novel class-AB architecture for single-stage operational amplifiers is presented. The structure employs a switchedcapacitor level shifter to provide a signal-dependent current in the current source of the common-source amplifier. Applying this pseudo-class-AB approach to a telescopic-cascode op-amp enhances the effective values of the slew rate and the transconductance and thus the op-amp speed

A prototype bandpass Sigma-delta modulator employing crystal resonator

10.1007/s10470-005-3013-zAnalog Integrated Circuits and Signal Processing443261-269AICP

A reconfigurable dual-mode tracking SAR ADC without analog subtraction

Abstract In this contribution, it is proposes to limit the quantization search space of a successive approximation analog-to-digital converter through an analytic derivation of maximum possible sample-to-sample variation. The presented example design of the proposed ADC is an 8-bit 1MS/s ADC with SAR logic customized to incorporate this priori information while no modification has been required to the analog circuitry. In comparison to conventional SAR conversion, the proposed tracking approach yields significant reduction in total power consumption in oversampling mode. The power savings are due to the reduced number of SAR cycles, and voltage variation minimization across DAC capacitors. The design is reconfigurable both to conventional SAR sampling and the proposed tracking scheme. The approach is attractive for SAR ADCs embedded in very low power micro-controllers

ADC-assisted random sampler architecture for efficient sparse signal acquisition

Abstract A method for sampling Fourier sparse signals for efficient implementation of analog-to-information converters is proposed. The solution reconstructs Nyquist rate high-resolution signal from Nyquist rate low-resolution and sub-Nyquist rate high-resolution samples. For implementation, an architecture based on customized reconfigurable successive approximation register analog-to-digital converter is proposed, simulated, and demonstrated. The power consumption with a 90-nm CMOS process is less than 26 μW with 1-Msample/s rate in reconfigurable 3/10-bit mode. The number of floating point operations per second needed for signal recovery is less than 2% required by the orthogonal matching pursuit algorithm. The functionality of the solution has been verified with an experimental system