Evaluation of a Pound Net Leader Designed to Reduce Sea Turtle Bycatch

Offshore pound net leaders in the southern portion of Chesapeake Bay in Virginia waters were documented to incidentally take protected loggerhead, Caretta caretta, and Kemp’s ridley, Lepidochelys kempii, sea turtles. Because of these losses, NOAA’s National Marine Fisheries Service (NMFS) in 2004 closed the area to offshore pound net leaders annually from 6 May to 15 July and initiated a study of an experimental leader design that replaced the top two-thirds of the traditional mesh panel leader with vertical ropes (0.95 cm) spaced 61 cm apart. This experimental leader was tested on four pound net sites on the eastern shore of Chesapeake Bay in 2004 and 2005. During the 2 trial periods, 21 loggerhead and Kemp’s ridley sea turtles were found interacting with the control leader and 1 leatherback turtle, Dermochelys coriacea, was found interacting with the experimental leader. Results of a negative binomial regression analysis comparing the two leader designs found the experimental leader significantly reduced sea turtle interactions (p=0.03). Finfish were sampled from the pound nets in the study to assess finfish catch performance differences between the two leader designs. Although the conclusions from this element of the experiment are not robust, paired t-test and Wilcoxon signed rank test results determined no significant harvest weight difference between the two leaders. Kolmogorov-Smirnov tests did not reveal any substantive size selectivity differences between the two leaders

Regional variation in digital cushion pressure in the forefeet of horses and elephants

In this study, we seek to understand how the digital cushion morphologies evident in horse and elephant feet influence internal and external foot pressures. Our novel use of invasive blood pressure monitoring equipment, combined with a pressure pad and force plate, enabled measurements of (ex vivo) digital cushion pressure under increasing axial loads in seven horse and six elephant forefeet. Linear mixed effects models (LMER) revealed that internal digital cushion pressures increase under load and differ depending on region; elephant feet experienced higher magnitudes of medial digital cushion pressure, whereas horse feet experienced higher magnitudes of centralised digital cushion pressure. Direct comparison of digital cushion pressure magnitudes in both species, at equivalent loads relative to body weight, revealed that medial and lateral pressures increased more rapidly with load in elephant limbs. Within the same approximate region, internal pressures exceeded external, palmar pressures (on the sole of the foot), supporting previous Finite Element (FE) predictions. High pressures and large variations in pressure may relate to the development of foot pathology, which is a major concern in horses and elephants in a captive/domestic environment

Loop Coalescing and Scheduling for Barrier MIMD Architectures

Barrier MIMDs are asynchronous Multiple Instruction stream Multiple Data stream architectures capable of parallel execution of variable execution time instructions and arbitrary control flow (e.g., while loops and calls); however, they differ from conventional MlMDs in that the need for run-time synchronization is significantly reduced. This work considers the problem of scheduling nested loop structures on a barrier MIMD. The basic approach employs loop coalescing, a technique for transforming a multiply-nested loop into a single loop. Loop coalescing is extended to nested triangular loops, in which inner loop bounds are functions of outer loop indices. Also, a more efficient scheme to generate the original loop indices from the coalesced index is proposed for the case of constant loop bounds. These results are general, and can be applied to extend previous work using loop coalescing techniques. We concentrate on using loop coalescing for scheduling barrier MIMDs, and show how previous work in loop transformations [Wol89], [Pol88] and linear scheduling theory [ShF88], rShO901 cart be applied to this problem

A Cocoon Romance : Fuzzy - Wuzzy Caterpiller

https://digitalcommons.library.umaine.edu/mmb-vp/5770/thumbnail.jp

Hardware Barrier Synchronization: Static Barrier MIMD (SBM)

In this paper, we give the design, and performance analysis, of a new, highly efficient, synchronization mechanism called “Static Barrier MIMD” or “SBM.” Unlike traditional barrier synchronization, the proposed barriers are designed to facilitate the use of static (compile-time) code scheduling for eliminating some synchronizations. For this reason, our barrier hardware is more general than most hardware barrier mechanisms, allowing any subset of the processors to participate in each barrier. Since code scheduling typically operates on fine-grain parallelism, it is also vital that barriers be able to execute in a small number of clock ticks. The SBM is actually only one of two new classes of barrier machines proposed to facilitate static code scheduling; the other architecture is the “Dynamic Barrier MIMD,” or “DBM,” which is described in a companion paper1. The DBM differs from the SBM in that the DBM employs more complex hardware to make the system less dependent on the precision of the static analysis and code scheduling; for example, an SBM cannot efficiently manage simultaneous execution of independent parallel programs, whereas a DBM can

Static Scheduling for Barrier MIMD Architectures

Barrier MIMDs are asynchronous Multiple Instruction stream Multiple Data stream architectures capable of parallel execution of variable-execution-time instructions and arbitrary control flow (e.g., w h ile loops and calls); however, they differ from conventional MIMDs in that the need for run-time synchronization is significantly reduced. Whenever a group of processors within a barrier MIMD encounters a synchronization point (barrier), static timing constraints become precise, hence, conceptual synchronizations between the processors often can be statically resolved with zero cost — as in a SIMD or VLIW and using similar compiler technology. Unlike these machines, however, as execution continues past the synchronization point the accuracy within which the compiler can track the relative timing between processors is reduced. Where this imprecision becomes too large, the compiler simply inserts a synchronization barrier to insure that timing imprecision at that point is zero, and again employs static, implicit synchronization. This paper describes new scheduling and barrier placement algorithms for barrier MIMDs that are based loosely on the list scheduling approach employed for VLIWs [Elli85]. In addition, the experimental results from scheduling more than 3500 synthetic benchmark programs for a parameterized barrier MIMD machine are presented