Nanostructured porous materials form Micro- and nano-electronics applications

This thesis work presents new research on porous silicon technologies for the heterogeneous integration on silicon platforms, as a key enabling technology for future 3D integrated systems. Porous silicon can be obtained with CMOS compatible processes on localized area on silicon wafer and, due to its tunable electrical, mechanical and thermal characteristics is an effective buffer material. Moreover, macroporous morphologies of porous silicon can can be exploited for the realization of “bed-of-nails” type through wafer interconnects, paving the way to high density, low-cost, through silicon vias. This work is divided in three parts: the first part introduces porous silicon, summarizes the available literature and presents process characterization for the porous layers obtained in this work and their properties; the second part describes the layer transfer technology and the buried cavities technologies developed in this work using the porous layers presented in the previous part; the last part introduces two applications of the layer transfer technology: compliant contacts and integrated physically small antennas

FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs

The semiconductor industry continues to grow and innovate; however, companies are facing challenges in growing their workforce with skilled technicians and engineers. To meet the demand for well-trained workers worldwide, innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem are of utmost importance. FOSS CAD/EDA tools combined with free and open-access PDKs can serve as a new platform for bringing together IC design newbies, enthusiasts, and experienced mentors

First integration of MOSFET band-to-band-tunneling current in BSIM4

Static leakage currents represent a major issue in nano-scale CMOS. In digital VLSI circuits, the most relevant contributions to the overall leakage current are subthreshold conduction, gate current and band-to-band-tunneling (BTBT) current, which flows from drain/source to bulk through the reverse biased diffusion junctions. While the latter has been recognized as an important effect in digital nano-CMOS, yet no compact model of it has ever been included in the industry-standard device model BSIM4. In this work, we show that the lack of a BTBT current model leads to discrepancies between SPICE and device-level simulations and that adding a BTBT current source into BSIM4 DC model can correct this. The new current source follows a widely accepted physical model of the BTBT phenomenon with a rectangular junction approximation. Test case results show a good agreement between the new circuit-level simulations and the device-level extracted currents. © 2011 Elsevier Ltd