Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Analysis of the high-speed polysilicon photodetector in fully standard CMOS technology

A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which gure was limited by the measurement equipment. The high intrinsic (physical) bandwidth is due to a short excess carrier lifetime. The external (electrical) bandwidth is also high because of a very small parasitic capacitance (<0.1 pF). This is the best bandwidth performance among all reported diodes designed in a standard CMOS. The quantum efficiency of this poly photodiode is 0.2% due to the very small light sensitive diode volume. The diode active area is limited by a narrow depletion region and its depth by the technology

D/A Resolution Impact on a Poly-phase Multipath Transmitter

In recent publications the Poly-phase multipath technique has been shown to produce a clean output spectrum for a power upconverter (PU) architecture. The technique utilizes frequency independent phase shifts before and after a nonlinear element to cancel out the harmonics and sidebands due to the nonlinearity. A major advantage of this technique is that it circumvents the need to use dedicated RF filters which makes it a potential candidate for cognitive radio transmitters. This paper addresses the requirements on the digital and mixed signal part of such a transmitter. An architecture is proposed based on complex multiplication which can be used to generate the digital multiphase signals required by the multipath technique. Due to equal phase difference of all the paths the same digital hardware could be utilized for carrying out all the phase shifts. When the digital signals pass through a D/A converter which doesn’t have a reconstruction filter, the output in this case would be amplitude discrete like that of a zero order hold. The spectrum of this amplitude discrete signal would have distortion components in it. This can be termed as quantization distortion but now in the context of limited D/A resolution. The multipath technique’s effect on harmonic cancellation, in the presence of such a quantization distortion is explored in this paper. It is shown through simulation that when using ideal phase shifts the multipath technique is able to cancel most of the harmonics produced by an amplitude discrete representation of pure sinusoids. When (upconversion) mixers are used for the second set of phase shifts then with multipath the highest quantization spurs go down with roughly 8db/bit for a single tone and around 10db/bit for two tone inputs

Trends and challenges in VLSI technology scaling towards 100 nm

Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Finally, the tutorial will review the test challenges for the 100nm technology node due to increased clock frequency and power consumption (both active and passive) and present several potential solution

Double resonant absorption measurement of acetylene symmetric vibrational states probed with cavity ring down spectroscopy

A novel mid-infrared/near-infrared double resonant absorption setup for studying infrared-inactive vibrational states is presented. A strong vibrational transition in the mid-infrared region is excited using an idler beam from a singly resonant continuous-wave optical parametric oscillator, to populate an intermediate vibrational state. High output power of the optical parametric oscillator and the strength of the mid-infrared transition result in efficient population transfer to the intermediate state, which allows measuring secondary transitions from this state with a high signal-to-noise ratio. A secondary, near-infrared transition from the intermediate state is probed using cavity ring down spectroscopy, which provides high sensitivity in this wavelength region. Due to the narrow linewidths of the excitation sources, the rovibrational lines of the secondary transition are measured with sub-Doppler resolution. The setup is used to access a previously unreported symmetric vibrational state of acetylene, $\nu_1+\nu_2+\nu_3+\nu_4^1+\nu_5^{-1}$ in the normal mode notation. Single-photon transitions to this state from the vibrational ground state are forbidden. Ten lines of the newly measured state are observed and fitted with the linear least-squares method to extract the band parameters. The vibrational term value was measured to be at 9775.0018(45) $\text{cm}^{-1}$, the rotational parameter $B$ was 1.162222 $\text{cm}^{-1}$, and the quartic centrifugal distortion parameter $D$ was 3.998(62)$\times 10^{-6} \text{cm}^{-1}$, where the numbers in the parenthesis are one-standard errors in the least significant digits

A 1.2V 10μW NPN-Based Temperature Sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from −70°C to 125°C

This paper describes a temperature sensor realized in a 65nm CMOS process with a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ) from –70°C to 125°C. This represents a 10-fold improvement in accuracy compared to other deep-submicron temperature sensors [1,2], and is comparable with that of state-of-the-art sensors implemented in larger-featuresize processes [3,4]. The sensor draws 8.3μA from a 1.2V supply and occupies an area of 0.1mm2, which is 45 times less than that of sensors with comparable accuracy [3,4]. These advances are enabled by the use of NPN transistors as sensing elements, the use of dynamic techniques i.e. correlated double sampling (CDS) and dynamic element matching (DEM), and a single room-temperature trim

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes

A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 ¿W at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.\u

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Kansen voor pluimveemest

Pluimveemest is een hoogwaardige meststof met veel stikstof, fosfaat en kali. De hoge fosfaatwaarden maken de afzet echter moeilijk. Het project ‘Kippenmest & Kringloop’ was vooral bedoeld om te onderzoeken hoe de stikstof-fosfaat verhouding kan worden aangepast, zodat deze mest beter bruikbaar is voor de teelt van gewassen. In dit BioKennisbericht vindt u informatie over de verschillende mogelijkheden